1、NOVEMBER 2016 DDR4 Data Buffer Defintion (DDR4DB01) JEDEC STANDARD JEDEC SOLID STATE TECHNOLOGY ASSOCIATION JESD82-32NOTICE JEDEC standards and publications contain material that has been prepared, reviewed, and approved through the JEDEC Board of Directors level and subsequently reviewed and approv
2、ed by the JEDEC legal counsel. JEDEC standards and publications are designed to serve the public interest through eliminating misunderstandings between manufacturers and purchasers, facilitating interchangeability and improvement of products, and assisting the purchaser in selecting and obtaining wi
3、th minimum delay the proper product for use by those other than JEDEC members, whether the standard is to be used either domestically or internationally. JEDEC standards and publications are adopted without regard to whether or not their adoption may involve patents or articles, materials, or proces
4、ses. By such action JEDEC does not assume any liability to any patent owner, nor does it assume any obligation whatever to parties adopting the JEDEC standards or publications. The information included in JEDEC standards and publications represents a sound approach to product specification and appli
5、cation, principally from the solid state device manufacturer viewpoint. Within the JEDEC organization there are procedures whereby a JEDEC standard or publication may be further processed and ultimately become an ANSI standard. No claims to be in conformance with this standard may be made unless all
6、 requirements stated in the standard are met. Inquiries, comments, and suggestions relative to the content of this JEDEC standard or publication should be addressed to JEDEC at the address below, or refer to www.jedec.org under Standards and Documents for alternative contact information. Published b
7、y JEDEC Solid State Technology Association 2016 3103 North 10th Street Suite 240 South Arlington, VA 22201-2107 This document may be downloaded free of charge; however JEDEC retains the copyright on this material. By downloading this file the individual agrees not to charge for or resell the resulti
8、ng material. PRICE: Contact JEDEC Printed in the U.S.A. All rights reserved PLEASE! DONT VIOLATE THE LAW! This document is copyrighted by JEDEC and may not be reproduced without permission. For information, contact: JEDEC Solid State Technology Association 3103 North 10th Street Suite 240 South Arli
9、ngton, V A 22201-2107 or refer to www.jedec.org under Standards-Documents/Copyright Information.(This page is intentionally left blank)JEDEC Standard No. 82-32 DDR4 DATA BUFFER DEFINITION (DDR4DB01) Contents -i- 1 Scope .1 2 Device standard1 2.1 Description.1 2.1.1 Power-on Initialization 1 2.1.2 Da
10、ta Buffer Control Bus 3 2.1.3 Dedicated Signals 4 2.1.4 Dual Frequency Support 7 2.1.5 Input Clock Frequency Change .7 2.1.6 Command Sequences.8 2.1.7 Command Sequence Descriptions .10 2.1.8 Training Support Features .25 2.1.9 Transparent Mode 33 2.1.10 ZQ Calibration .34 2.2 Mechanical Outline35 2.
11、3 Pinout .35 2.4 Terminal Functions .36 2.5 Buffer Control Words 36 2.5.1 BCW Decoding37 2.5.2 BC00 - Host Interface DQ RTT_NOM Termination Control Word .40 2.5.3 BC01 - Host Interface DQ RTT_WR Termination Control Word 40 2.5.4 BC02 - Host Interface DQ RTT_PARK Termination Control Word40 2.5.5 BC03
12、 - Host Interface DQ Driver Control Word 41 2.5.6 BC04 - DRAM Interface MDQ Termination Control Word .41 2.5.7 BC05 - DRAM Interface MDQ Driver Control Word 41 2.5.8 BC06 - Command Space Control Word42 2.5.9 BC07 - Rank Presence Control Word42 2.5.10 BC08 - Rank Number & Selection Control Word.42 2.
13、5.11 BC09 - Power Saving Settings Control Word .43 2.5.12 BC0A - LRDIMM Operating Speed44 2.5.13 BC0B - Operating Voltage Control Word.45 2.5.14 BC0C - Buffer Training Control Word 45 2.5.15 BC0E - Parity and Sequence Error Control Word45 2.5.16 BC0F - Error Status Word 46 2.5.17 F7:0BC7x - Function
14、 Space Selector Control Word.46 2.5.18 F0BC1x - Buffer Configuration Control Word46 2.5.19 F0BC6x - Fine Granularity LRDIMM Operating Speed.48 2.5.20 F0BCCx - Lower/Upper Nibble Additional Cycles DRAM Interface Receive Enable Control Word for Rank 0.50 2.5.21 F0BCDx - Lower/Upper Nibble Additional C
15、ycles DRAM Interface Write Leveling Control Word for Rank 0 .50 2.5.22 6F0BCEx - Lower/Upper Nibble Additional Cycles DRAM Interface Receive Enable Control Word for Rank 2 .51 2.5.23 F0BCFx - Lower/Upper Nibble Additional Cycles DRAM Interface Write Leveling Control Word for Rank 251 2.5.24 F1BCCx -
16、 Lower/Upper Nibble Additional Cycles DRAM Interface Receive Enable Control Word for Rank 1.52 2.5.25 F1BCDx - Lower/Upper Nibble Additional Cycles DRAM Interface Write Leveling Control Word for Rank 1 .52 2.5.26 F1BCEx - Lower/Upper Nibble Additional Cycles DRAM Interface Receive Enable Control Wor
17、d for Rank 3 .53 2.5.27 F1BCFx - Lower/Upper Nibble Additional Cycles DRAM Interface Write Leveling Control Word for Rank 353 2.5.28 F3:0BC2x/F3:0BC3x - Lower/Upper Nibble DRAM Interface Receive Enable Training Control Word (per rank)54 2.5.29 F3:0BC4x - Lower Nibble MDQS Read Delay Control Word .55
18、 2.5.30 F3:0BC5x - Upper Nibble MDQS Read Delay Control Word56 2.5.31 F3:0BC8x - Lower Nibble MDQ-MDQS Write Delay Control Word .57 2.5.32 F3:0BC9x - Upper Nibble MDQ-MDQS Write Delay Control Word .58 2.5.33 F3:0BCAx/F3:0BCBx - Lower/Upper Nibble DRAM Interface Write Leveling Control Word (per rank)
19、59 2.5.34 F4BC0x F4BC6x - MRS Snooped Settings .60 2.5.35 F5BC0x F5BC3x & F6BC0x F6BC3x - Upper and Lower Multi Purpose Registers .60 2.5.36 F5BC5x - Host Interface VREF Control Word .61 2.5.37 F5BC6x - DRAM Interface VREF Control Word .62 2.5.38 F6BC4x - Buffer Training Configuration Control Word.6
20、3 2.5.39 F6BC5x - Buffer Training Status Word.63 2.5.40 F7BC0x F7BC3x - Error Log Register .64 2.5.41 F7:4BC8x - MDQ0/4 Read Delay Control Word 65JEDEC Standard No. 82-32 DDR4 DATA BUFFER DEFINITION (DDR4DB01) Contents (contd) -ii- 2.5.42 F7:4BC9x - MDQ1/5 Read Delay Control Word 66 2.5.43 F7:4BCAx
21、- MDQ2/6 Read Delay Control Word .67 2.5.44 F7:4BCBx - MDQ3/7 Read Delay Control Word .68 2.5.45 F7:4BCCx - MDQ0/4-MDQS Write Delay Control Word69 2.5.46 F7:4BCDx - MDQ1/5-MDQS Write Delay Control Word .70 2.5.47 F7:4BCEx - MDQ2/6-MDQS Write Delay Control Word71 2.5.48 F7:4BCFx - MDQ3/7-MDQS Write D
22、elay Control Word 72 2.6 Logic Diagram .73 3 Absolute maximum ratings .74 4 Input AC and DC Specifications.75 4.1 DQ Input Receiver Specifications 76 4.2 MDQ Input Receiver Specifications80 4.3 CTRL Input Receiver Specifications84 4.4 AC and DC Logic Input Levels for Differential Signals .88 4.4.1 D
23、ifferential signal definition88 4.4.2 Differential swing requirements for BCK_t / BCK_c .88 4.4.3 Single-ended requirements for BCK_t / BCK_c .89 4.5 Differential Input Cross point voltage .90 4.6 Differential Input Slew Rate Definitions for BCK 93 4.7 Overshoot and Undershoot Specifications.94 4.8
24、DQ Vref Specifications96 5 Output AC and DC Specifications .101 5.1 MDQ/MDQS Output Driver DC Electrical Characteristics.101 5.2 ALERT_n Output Driver DC Electrical Characteristic.102 5.3 Single-ended AC & DC Output Levels .102 5.4 Differential AC Output Levels 103 5.5 Single-Ended Output Slew Rate
25、104 5.6 Differential Output Slew Rate .105 5.7 Differential Output Cross Point Voltage .106 5.8 On-Die Termination (ODT) Levels and I-V Characteristics .107 6 DC specifications, IDD Measurement Conditions 110 6.1 DC Electrical Characteristics.110 6.2 IDD Specification Parameters and Test Conditions
26、110 7 Input/Output Capacitance 123 8 Timing Requirements 125 8.1 Clock Specification125 8.1.1 Definition for tCK(avg), nCK and tCH(avg) and tCL(avg) 125 8.1.2 Definition for tCK(abs), tCH(abs) and tCL(abs) .125 8.1.3 Definition for tJIT(per) 126 8.1.4 Definition for tJIT(cc)126 8.1.5 Definition for
27、duty cycle jitter tJIT(duty) 126 8.1.6 Definition for tERR(nper)126 8.2 Clock Requirements.127 8.3 Input Timing Requirements .129 8.4 Host and DRAM Interface Preamble and Postamble Timing Requirements 130 8.4.1 txPRE Calculation131 8.4.2 txPST Calculation 132 8.5 Output Timing Requirements 133 8.5.1
28、 READ Output Timing Definitions.135 8.5.2 WRITE Output Timing Definitions.137 8.6 Package Rank to Package Rank Timing Requirements.138 8.7 MREP and HWL Strobe Sampling Output Delay Parameters 138 8.8 MRD Data Comparator Output Delay Parameters 138 9 Test circuits and switching waveforms 139 9.1 Para
29、meter measurement information.139 9.2 ALERT_n output load circuit and voltage measurement information 140 10 References to other applicable documents 141JEDEC Standard No. 82-32 Page 1 DDR4 DATA BUFFER DEFINITION (DDR4DB01) (From JEDEC Board Ballot JCB-14-12, formulated under the cognizance of the J
30、C-40.4 Subcommittee on Registered & Fully Buffered Memory Support Logic.) 1S c o p e This standard defines standard specifications for features and functionality, DC and AC interface parameters and test loading for definition of the DDR4 data buffer for driving DQ and DQS nets on DDR4 LRDIMM applica
31、tions. Any TBDs as of this document, are under discussion by formulating committee. The purpose is to provide a standard for the DDR4DB01 (see Note) logic device, for uniformity, multiplicity of sources, elimination of confusion, ease of device specification, and ease of use. NOTE The designation DD
32、R4DB01 refers to the part designation of a series of commercial logic parts common in the industry. This designation is normally preceded by a series of manufacturer specific characters to make up a complete part designation. 2 Device standard 2.1 Description This dual 4-bit bidirectional data regis
33、ter with differential strobes is designed for 1.2 V V DDoperation. The device has a dual 4-bit host bus interface that is connected to a memory controller and a dual 4-bit DRAM interface that is connected to two x4 DRAMs. It also has an input-only control bus interface that is connected to a DDR4 Re
34、gister. This interface consists of a 4-bit control bus, two dedicated control signals, a voltage reference input and a differential clock input. All DQ inputs are pseudo-differential with an internal voltage reference. All DQ outputs are V DDterminated drivers optimized to drive single or dual termi
35、nated traces in DDR4 LRDIMM applications. The differential DQS strobes are used to sample the DQ inputs and are regenerated in the DDR4DB01 for driving out the DQ outputs on the opposite side of the device. The clock inputs BCK_t and BCK_c are used to sample the control inputs BCOM3:0, BCKE and BODT
36、. The BCOM3:0 inputs are used to write device internal control registers. The buffer control word (BCW) mechanism is described in more detail in 2.5. The DDR4DB01 also supports dedicated pins for ZQ calibration and for parity error alerts. 2.1.1 Power-on Initialization To ensure defined outputs from
37、 the register before a stable clock has been supplied, the memory buffer must enter the reset state during power-up. After the voltage ramp, stable power is held for a minimum of 200 s in the RESET state (i.e., the BCK_t/BCK_c inputs are held LOW and the BCKE input is held HIGH). In the RESET state
38、all other input receivers are disabled, and can be left floating. In the RESET state, all control registers are restored to their default states (which is “0”, except when explicitly defined otherwise). All outputs must float. In the RESET state the data buffer is in low power state and host interfa
39、ce or DRAM interface termination is disabled. With a falling edge of the BCKE input, the data buffer transitions to the clock stopped power down mode. A certain period of time (t ACT =16 t CK ) before the BCKE input is pulled LOW the reference voltage BVrefCA needs to be stable within specification.
40、 With stable clock input signals BCK_t/BCK_c and BCKE still held LOW, the buffer transitions into the equivalent of CKE power down mode. JEDEC Standard No. 82-32 Page 2 2.1.1.1 Clock Stabilization Time t DLLK During DLL stabilization time t DLLKthe data buffer is not fully operational. In ensure cor
41、rect operation, some rules apply to the inputs of the buffer: BCKE must remain LOW. BODT is kept at a stable valid logic level. These rules apply to any instance where stabilization time t DLLKis required: Exit from Reset state Exit from clock stop power down Changing clocking related registers Chan
42、ging input clock frequency during boot or run time Since the data buffer has not reached a stable state the termination on the host interface will be undefined before the end of the stabilization time. After reset and after the DLL stabilization time (t DLLK ) the DB must meet the input setup- and h
43、old specification, as well as accept and transfer input signals to the corresponding outputs. 2.1.1.2 Reset Initialization with Stable Power The timing diagram depicts the initialization sequence with stable power and clock. This will apply to the situation when we have a soft reset in the system. T
44、he data buffer remains in the RESET state for a minimum of 16 * t CK(i.e., BCK_t/BCK_c are held LOW (i.e., below V IL(static) ) and BCKE input is held HIGH for that long). After initialization, the host needs to write to those control registers in the RCD and DB whose contents need to be changed bef
45、ore it can proceed to the DRAM initialization.JEDEC Standard No. 82-32 Page 3 2.1.2 Data Buffer Control Bus This section describes the signals used in the DDR4 LRDIMM control bus that connects the DDR4 Register with each of the nine DDR4 data buffers (DDR4DB01). 2.1.2.1 Control Bus Signals Table 1 L
46、ist of Signals for Data Buffer control Name Description Signal Count BCOM3:0 Data buffer command signals 4 BCKE Function of registered DCKE (dedicated non-encoded signal) 1 BODT Function of registered DODT (dedicated non-encoded signal) 1 BCK_t, BCK_c Input clock 2 BVrefCA Reference voltage for comm
47、and and control signals 1 To t a l 9 2.1.2.2 Command List Table 2 DDR4 Data Buffer Command Table Command Description BCOM3:0 Encoding WR Write BC4 or BC8 (fixed or on the fly) or BC10 (with CRC enabled) and send accessed rank ID and BL information in the next command time slot, followed by parity in
48、 the last command time slot. 1000 RD Read BC4 or BC8 (fixed or on the fly) and send accessed rank ID and BL information in the next command time slot, followed by parity in the last command time slot. 1001 MRS Write Send MRS Write bits snooped by DDR4 Register and the MRS ID in the fol- lowing six c
49、ommand time slots, followed by parity in the last command time slot. 1011 BCW Write Write buffer control word data in the next five command slots, followed by parity in the last command time slot. 1100 BCW Read Read buffer control word address in the four command slots, followed by parity in the last command time slot. 1101 RFU 1 1.RFU commands are treated as NOP commands for command sequence error detection Reserved for future use 1110 RFU 1 Reserved for future use 1111 NOP Idle, do nothing 1010JEDEC Standard No. 82-32 Page 4 2
