1、 IEC 62026-2 Edition 2.0 2008-01 INTERNATIONAL STANDARD NORME INTERNATIONALE Low-voltage switchgear and controlgear Controller-device interfaces (CDIs) Part 2: Actuator sensor interface (AS-i) Appareillage basse tension Interfaces appareil de commande-appareil (CDI) Partie 2: Interface capteur-actio
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16、visitez le FAQ du Service clients ou contactez-nous: Email: csciec.ch Tl.: +41 22 919 02 11 Fax: +41 22 919 03 00 IEC 62026-2 Edition 2.0 2008-01 INTERNATIONAL STANDARD NORME INTERNATIONALE Low-voltage switchgear and controlgear Controller-device interfaces (CDIs) Part 2: Actuator sensor interface (
17、AS-i) Appareillage basse tension Interfaces appareil de commande-appareil (CDI) Partie 2: Interface capteur-actionneur (AS-i) INTERNATIONAL ELECTROTECHNICAL COMMISSION COMMISSION ELECTROTECHNIQUE INTERNATIONALE XK ICS 29.130.20 PRICE CODE CODE PRIX ISBN 2-8318-1059-8 Registered trademark of the Inte
18、rnational Electrotechnical Commission Marque dpose de la Commission Electrotechnique Internationale 2 62026-2 IEC:2008 CONTENTS FOREWORD.7 1 Scope and object9 2 Normative references.9 3 Terms, definitions, symbols and abbreviations11 4 Classification18 4.1 Overview.18 4.2 Components and interfaces.1
19、9 5 Characteristics.21 5.1 Overview.21 5.2 Signal characteristics 21 5.3 Power and data distribution .23 5.4 AS-i topology and other components .25 5.5 Communication.27 5.6 AS-i single transactions.30 5.7 AS-i combined transactions .42 5.8 AS-i error detection .59 6 Product information 60 6.1 Instru
20、ctions for installation, operation and maintenance 60 6.2 Profiles60 6.3 Marking.61 7 Normal service, mounting and transport conditions.62 7.1 Normal service conditions .62 7.2 Conditions during transport and storage 62 7.3 Mounting.63 8 Constructional and performance requirements63 8.1 AS-i transmi
21、ssion medium.63 8.2 AS-i power supply.66 8.3 AS-i repeater and other components .68 8.4 AS-i slave69 8.5 AS-i master.85 8.6 Electromagnetic compatibility (EMC) .89 9 Tests90 9.1 Kinds of tests90 9.2 Test of transmission medium.91 9.3 Test of the AS-i power supply92 9.4 Test of an AS-i repeater and o
22、ther components.98 9.5 Test of an AS-i slave .106 9.6 Test of a AS-i master.120 Annex A (normative) Slave profiles 135 Annex B (normative) Master profiles 213 Figure 1 AS-i components and interfaces.19 Figure 2 Transmission coding 21 Figure 3 Receiver requirements .23 Figure 4 AS-i power supply 24 6
23、2026-2 IEC:2008 3 Figure 5 Equivalent schematic of symmetrization and decoupling circuit 25 Figure 6 Model of the AS-i transmission medium26 Figure 7 Transactions 28 Figure 8 Master and slave pause as viewed from master/slave point of view28 Figure 9 Representation of the master pause.29 Figure 10 S
24、tructure of a master request.31 Figure 11 Structure of a slave response.34 Figure 12 Structure of a data exchange request (top: standard address mode; bottom: extended address mode)34 Figure 13 Structure of the slave response (Data_Exchange)35 Figure 14 Structure of the Write_Parameter request (top:
25、 standard addressing mode; bottom: extended addressing mode) .35 Figure 15 Structure of the slave response (Write_Parameter) 35 Figure 16 Structure of the Address_Assignment request36 Figure 17 Structure of the slave response (Address_Assignment)36 Figure 18 Structure of the Write_Extended_ID-Code_1
26、 request .36 Figure 19 Structure of the slave response (Write_Extended_ID-Code_1) .36 Figure 20 Structure of the Reset_Slave request (top: standard addressing mode; bottom: extended addressing mode) .37 Figure 21 Structure of the slave response (Reset_Slave).37 Figure 22 Structure of the Delete_Addr
27、ess request (top: standard addressing mode; bottom: extended addressing mode) .37 Figure 23 Structure of the slave response (Delete_Address)37 Figure 24 Structure of the Read_I/O_Configuration request (top: standard addressing mode; bottom: extended addressing mode).38 Figure 25 Structure of the sla
28、ve response (Read_I/O_Configuration) .38 Figure 26 Structure of Read_Identification_Code request (top: standard addressing mode; bottom: extended addressing mode).39 Figure 27 Structure of the slave response (Read_Identification_Code) 39 Figure 28 Structure of Read_Extended_ID-Code_1/2 Request (top:
29、 standard addressing mode; bottom: extended addressing mode).40 Figure 29 Structure of the slave response Read_Extended_ID-Code_1/2.40 Figure 30 Structure of Read_Status request (top: standard addressing mode; bottom: extended addressing mode) .41 Figure 31 Structure of the slave response (Read_Stat
30、us) 41 Figure 32 Structure of R1 request (top: standard addressing mode; bottom: extended addressing mode)41 Figure 33 Structure of the slave response (R1) 41 Figure 34 Structure of the Broadcast (Reset) request.42 Figure 35 Definition of the I/O data bits in combined transaction type 1 .43 Figure 3
31、6 Definition of the parameter bits in combined transaction type 1 43 Figure 37 Function sequence to Read ID, Read Diagnosis, Read Parameter in combined transaction type 1 .46 Figure 38 Function sequence to Write Parameter in combined transaction type 1 .47 4 62026-2 IEC:2008 Figure 39 Behaviour of t
32、he slave receiving a complete parameter string from the master in combined transaction type 148 Figure 40 Definition of the I/O data bits in combined transaction type 2 .49 Figure 41 Typical combined transaction type 2 signals as viewed by an oscilloscope (both data channels run idle) 50 Figure 42 T
33、ypical combined transaction type 2 signals (the master transmits the byte 10101011 Bin , the slave transmits 01110101 Bin ):51 Figure 43 Definition of the I/O data bits in combined transaction type 3 (4I/4O) .52 Figure 44 Definition and state diagram of the slave for combined transaction type 3 53 F
34、igure 45 Definition of the I/O data bits in combined transaction type 4 .55 Figure 46 AS-i standard cable for field installation .63 Figure 47 AS-i cabinet cable 64 Figure 48 Equivalent schematic of decoupling circuit .68 Figure 49 Decoupling circuit using a transformer .68 Figure 50 Typical timing
35、diagram for bidirectional input/outputs (D1, D3 = voltage level at respective data port).70 Figure 51 Main state diagram of an AS-i slave .73 Figure 52 Equivalent circuit of a slave for frequencies in the range of 50 kHz to 300 kHz 81 Figure 53 A slave with C3 to compensate for Z 1= Z 2 .82 Figure 5
36、4 Status indication on slaves.84 Figure 55 Structure of an AS-i master 86 Figure 56 Impedances of the master 87 Figure 57 Equivalent circuit of a master for frequencies in the range of 50 kHz to 300 kHz 87 Figure 58 Transmission control state machine .88 Figure 59 AS-i interfaces .91 Figure 60 Test
37、circuit for impedance measurement 92 Figure 61 Adjustable current sink (test circuit: NT_MODSENKE)93 Figure 62 Indicator (test circuit NT_IMPSYM) 93 Figure 63 Display (part of test circuit NT_IMPSYM) .94 Figure 64 Test set-up for symmetry measurement94 Figure 65 Test circuit for noise emission96 Fig
38、ure 66 Filter A (low-pass filter 0 Hz to 10 kHz) 96 Figure 67 Filter B (bandpass filter 10 kHz to 500 kHz) .96 Figure 68 Test circuit for start-up behaviour.97 Figure 69 Measurement set-up for impedance measurement .99 Figure 70 Test circuit for symmetry measurement 101 Figure 71 Test circuit (detai
39、l 1) 102 Figure 72 Test circuit (detail 2) 102 Figure 73 Bandpass (10 kHz . 500 kHz) .102 Figure 74 Procedure for symmetry test 103 Figure 75 Test circuit for interoperability in AS-i networks104 Figure 76 Additional test circuit 1 for repeater105 Figure 77 Additional test circuit 2 for repeater105
40、62026-2 IEC:2008 5 Figure 78 Test circuit .106 Figure 79 Test circuit decoupling network 107 Figure 80 Test circuit .108 Figure 81 Test circuit decoupling network 108 Figure 82 Test circuit (equivalent of 10 m AS-i line) .108 Figure 83 Test circuit (bandpass 10 kHz to 500 kHz) .109 Figure 84 Test ci
41、rcuit .110 Figure 85 Constant current source.110 Figure 86 Test circuit .112 Figure 87 Test circuit .114 Figure 88 Test circuit (detail 1) 114 Figure 89 Test circuit (detail 2) 115 Figure 90 Procedure for symmetry test 116 Figure 91 Test circuit AS-i network 117 Figure 92 Test circuit for safety rel
42、ated slaves .118 Figure 93 Test circuit for current consumption test.120 Figure 94 Decoupling network, ammeter and power supply120 Figure 95 Test circuit noise emission AS-i master121 Figure 96 Decoupling network122 Figure 97 Bandpass 10 kHz to 500 kHz .122 Figure 98 Equivalent circuit of the 10 m A
43、S-i line .122 Figure 99 Test circuit impedance measurement .125 Figure 100 Master connection for symmetry measurement.126 Figure 101 Test circuit symmetry measurement of the AS-i master 127 Figure 102 Bandpass 10 kHz to 500 kHz127 Figure 103 Procedure for symmetry test.128 Figure 104 Test circuit On
44、-delay .129 Figure 105 Oscillogram on-delay (example) .129 Figure 106 Block circuit diagram current consumption measurement of the AS-i master 130 Figure 107 Constant current source with trigger output (KONST_I) 130 Figure 108 Oscillogram current consumption (example) .130 Figure 109 Test circuit fo
45、r checking start-up operation.131 Figure 110 Test circuit for checking normal operation 132 Figure 111 Test circuit .134 Figure A.1 Definition of the extended ID2 code bits for S-7.3 .180 Figure A.2 Definition of the extended ID2 code bits for S-7.4 .184 Figure A.3 Data structure of the ID string (S
46、-7.4) .189 Figure A.4 Data structure of the diagnostic string (S-7.4).193 Figure A.5 Data structure of the parameter string (S-7.4).194 Figure A.6 Definition of the extended ID1 code bits for S-7.A.8 and S-7.A.9.204 Figure A.7 Connection of mechanical switches 211 6 62026-2 IEC:2008 Table 1 AS-i pow
47、er supply specifications .24 Table 2 Symmetrization and decoupling circuit specifications 25 Table 3 Bit strings of the master requests 31 Table 4 Master requests (standard addressing mode)32 Table 5 Master requests in the extended addressing mode33 Table 6 Bit strings of the slave responses34 Table
48、 7 I/O Codes (IN = Input; OUT = Output; TRI = Tristate; I/O = Input/Output or Bidirectional (B).39 Table 8 List of combined transaction types 42 Table 9 Data transfer from slave to master in combined transaction type 1 44 Table 10 Data transfer from master to slave in combined transaction type 1 44 Table 11 Definition of serial clock and data in combined transaction type 2 .50 Table 12 Data transfer in combined transaction type 2.50 Table 13 Definition of the ID2 code in combined tr
