1、ANSI INCITS 293-1996 (R2001)(formerly ANSI X3.293-1996 (R2001)for Information Technology Serial Storage Architecture Physical Layer 1 (SSA-PH1)ANSIX3.293-1996American National Standardfor Information Technology Serial Storage Architecture Physical Layer 1 (SSA-PH1)SecretariatInformation Technology I
2、ndustry CouncilApproved November 29, 1996American National Standards Institute, Inc.AbstractThis standard defines the physical layer of the Serial Storage Architecture (SSA). SSA defines aserial interface hierarchy to be used for purposes within its distance and performance characteris-tics, includi
3、ng but not limited to storage subsystems. This standard is intended to be used with anupper layer protocol e.g., SCSI-2 Protocol (SSA-S2P), and a transport layer e.g., TransportLayer 1 (SSA-TL1).AmericanNationalStandardApproval of an American National Standard requires review by ANSI that therequire
4、ments for due process, consensus, and other criteria for approval havebeen met by the standards developer.Consensus is established when, in the judgment of the ANSI Board of StandardsReview, substantial agreement has been reached by directly and materiallyaffected interests. Substantial agreement me
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6、e anyone, whether he has approved the standardsor not, from manufacturing, marketing, purchasing, or using products, processes,or procedures not conforming to the standards.The American National Standards Institute does not develop standards and will inno circumstances give an interpretation of any
7、American National Standard.Moreover, no person shall have the right or authority to issue an interpretation ofan American National Standard in the name of the American National StandardsInstitute. Requests for interpretations should be addressed to the secretariat orsponsor whose name appears on the
8、 title page of this standard.CAUTION NOTICE: This American National Standard may be revised orwithdrawn at any time. The procedures of the American National StandardsInstitute require that action be taken periodically to reaffirm, revise, or withdrawthis standard. Purchasers of American National Sta
9、ndards may receive currentinformation on all standards by calling or writing the American National StandardsInstitute.CAUTION: The developers of this standard have requested that holders of patents that may be required for theimplementation of the standard disclose such patents to the publisher. How
10、ever, neither the developers nor the publisherhave undertaken a patent search in order to identify which, if any, patents may apply to this standard. As of the date ofpublication of this standard, following calls for the identification of patents that may be required for the implementation ofthe sta
11、ndard, notice of one or more such claims has been received. By publication of this standard, no position is takenwith respect to the validity of this claim or of any rights in connection therewith. The known patent holder(s) has (have),however, filed a statement of willingness to grant a license und
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13、 implied that this is the only license that may be required to avoid infringement in the use of this standard.Published byAmerican National Standards Institute11 West 42nd Street, New York, New York 10036Copyright 1996 by Information Technology Industry Council (ITI)All rights reserved.No part of th
14、is publication may be reproduced in anyform, in an electronic retrieval system or otherwise,without prior written permission of ITI, 1250 Eye Street NW,Washington, DC 20005.Printed in the United States of AmericaiForeword .ivIntroductionviii1 Scope11.1 SSA-PH1 characteristics 11.2 SSA family of stan
15、dards .22 Normative references.23 Definitions, symbols, and abbreviations 33.1 Definitions .33.2 Symbols and abbreviations.44 Conventions 55 Modulation.56 Data rate .57 Electrical requirements 67.1 Line driver .87.2 Line receiver137.3 Line segment termination .167.4 Ground shift.167.5 Port connectio
16、n177.6 System level noise margin228 Interconnections 238.1 Internal connectors 238.2 Internal port connections 398.3 Internal options bay connections.418.4 Internal device power connections 428.5 External connections43Tables1 Sustained data rate and maximum distance 62 SSA physical interconnect sche
17、mes .63 Driver output spectral content.124 Driver system operating parameters .135 Driver test parameters136 Line driver operating requirements137 Receiver system operating parameters .158 Receiver test parameters .159 Receiver operating requirements 1610 Electrical requirements for line termination
18、1611 Internal connector options 2412 Pinouts for internal port device connectors39ContentsPageii13 Pinout for 4-line internal port device connections.4014 Pinout for 5-line internal port device connections.4015 Pinout for 6-line internal port device connections.4116 TTL input pin parameters4117 TTL
19、output pin parameters4118 Options connector pinouts4219 Power connector pinouts 4320 Pinout for external device connectors .4721 External cable pinouts4822 Transfer impedance requirements for external SSA connections48Figures1 Relationship of the SSA standards22 Electrical configuration for SSA seri
20、al links .73 Test points.74 SSA Port driver implementation example 95 Relationship between driver currents 96 Test environment for drivers .107 Test environment for driver spectral content118 Driver output spectral content.129 SSA driver pulse mask .1210 SSA receiver test environment1411 Receiver pu
21、lse mask 1412 Definition of ground shift.1713 Lines and line segments.1814 Port connection and port connection segments1915 Complex port connection2016 Port connection coupler2117 Complex port connection examples using PCCs2218 Internal unitized backplane connector overview.2619 Internal unitized ba
22、ckplane connector detail2720 Internal cable and backplane port connector detail 2821 Internal cable and backplane option connector detail.2822 Internal cable and backplane power connector detail .2923 Internal cable and backplane connector contact detail .3024 Internal cable and backplane connector
23、contact wipe detail .30Pageiii25 Internal cable and backplane port connector detail (2 ports shown) 3126 Internal cable and backplane option and power connector detail 3227 Internal unitized device connector overview 3328 Internal unitized device connector detail (top view)3429 Internal unitized dev
24、ice connector detail (end view) .3530 Internal device port connector detail .3631 Internal device options connector detail 3632 Internal device power connector detail 3733 Internal device connector retention detail3834 Internal device connector pin sequencing detail 3835 External device connector in
25、terface 4536 External cable connector interface4637 Typical construction of external cable .47AnnexesA Transfer impedance testing procedure 49B Internal connector testing procedure.55C External connector testing procedure65D Line fault detection scheme examples.75E Circuit for degrading signal ampli
26、tude and introducing common modelevels.76F Preferred test configurations for SSA links 78G Implementation guidelines79H Reference for copper, polymer dielectric, non-equalized SSA cableassemblies 82PageivForeword (This foreword is not part of American National Standard X3.293-1996.)This Serial Stora
27、ge Architecture Physical Layer 1 standard is designedto provide a physical layer acceptable to device vendors, looking for anevolution from parallel SCSI, and systems designers looking for opportuni-ties to exploit more fully the capabilities inherent to a serial bus.This standard was developed by T
28、ask Group X3T10.1 of AccreditedStandards Committee X3 during 1993-96. The standards approval processstarted in 1995. Annexes A through C are normative; annexes D through H are informativeannexes and are not part of the standard.Requests for interpretation, suggestions for improvement and addenda, or
29、defect reports are welcome. They should be sent to the X3 Secretariat,Information Technology Industry Council, 1250 Eye Street, NW, Suite 200,Washington, DC 20005-3922.This standard was processed and approved for submittal to ANSI byAccredited Standards Committee on Information Technology, X3.Commit
30、tee approval of the standard does not necessarily imply that allcommittee members voted for its approval. At the time it approved thisstandard, the X3 Committee had the following members:James D. Converse, ChairDonald C. Loughry, Vice-ChairKate McMillan, SecretaryOrganization Represented Name of Rep
31、resentativeAMP, Inc .Ben BennettEdward Kelly (Alt.)Apple Computer, Inc. David K. MichaelJerry Kellenbenz (Alt.)ATb) support for optical transducers that allow longer distance connections;c) the link makes optimum use of the physical medium by using full-duplex communication toavoid arbitration overh
32、ead and turn-around delay;d) full duplex communication achieves an aggregate 40 MB/sec bandwidth (20 MB/sec in eachdirection) between two ports;e) the cables and connectors are physically compatible with small form factor devices;f) device connector capable of mating with both backplanes and cables;
33、g) an electrically balanced design that reduces EMI and crosstalk;h) a measurement scheme focusing on interoperability at separable connectors without requiringany internal physical access.ANSI X3.293-199621.2 SSA family of standardsThe relationships of the SSA family of standards is illustrated in
34、figure 1.1.2.1 SSA-S2PSerial Storage Architecture - (SSA-S2P) SCSI-2 Protocol defines the SCSI-2 Protocol used to run ontop of the SSA transport layers 1 or 2.1.2.2 SSA-S3PSerial Storage Architecture - (SSA-S3P) SCSI-3 Protocol defines the SCSI-3 Protocol used to run ontop of the SSA transport layer
35、 2.1.2.3 SSA-TL1Serial Storage Architecture - (SSA-TL1) Transport Layer 1 defines the Transport layer that runs SSA-S2P and runs on SSA-PH1.1.2.4 SSA-TL2Serial Storage Architecture - (SSA-TL2) Transport Layer 2 defines the Transport layer that runs SSA-S2P and SSA-S3P and run on SSA-PH1 or SSA-PH2.1
36、.2.5 SSA-PH1Serial Storage Architecture - (SSA-PH1) Physical Layer 1 defines the Physical layer that runs SSA-TL1 and SSA-TL2, and consists of the electrical characteristics of the interface and the connectors.1.2.6 SSA-PH2Serial Storage Architecture - (SSA-PH2) Physical Layer defines the Physical l
37、ayer that runs SSA-TL2,and consists of the electrical characteristics of the interface and the connectors.2 Normative referencesThe following standards contain provisions which, through reference in this text, constitute provisionsof this American National Standard. At the time of publication, the e
38、ditions indicated were valid. Allstandards are subject to revision, and parties to agreements based on this American NationalStandard are encouraged to investigate the possibility of applying the most recent editions of theFigure 1 - Relationship of the SSA standardsANSI X3.293-19963standard listed
39、below. Members of IEC and ISO maintain registers of currently valid InternationalStandards, and ANSI maintains registers for American National Standards.ANSI X3.294-1996, Information technology Serial Storage Architecture SCSI-2 Protocol (SSA-S2P)ANSI X3.295-1996, Information technology Serial Stora
40、ge Architecture Transport Layer 1 (SSA-TL1)ANSI/EIA 364-C-1994, Parts 13, 20, 21, 23, 31, 41, and 46- Electrical Connector/Socket TestProcedures Including Environmental ClassificationsIEC 512: Electromechanical components for electronic equipment; basic testing procedures andmeasuring methods 1)IEC
41、512-4 (1976) Part 4 - Dynamic stress tests 1)IEC 512-5 (1992) Part 5 - Impact tests (free components). static load tests (fixed components),endurance tests and overload tests 1)IEC 512-6 (1984) Part 6 - Climatic tests and soldering tests 1)IEC 512-7 (1993) Part 7 - Mechanical operating tests and sea
42、ling tests 1)IEC 512-11-7 (1996) Part 11 - Climatic tests - Test 11g: Flowing mixed gas corrosion test 1)IEC 801 - Environmental testing, 19881)3 Definitions, symbols, and abbreviations3.1 Definitions3.1.1 application: A process that is communicating via the link.3.1.2 Cable: A uniform media between
43、 connectors containing the four conductors required for twolines.3.1.3 Cable Assembly: A cable with connectors, backshells and retention schemes on each end.3.1.4 character: A sequence of 10 encoded bits that represents a data byte or a protocol function.3.1.5 Complex port connection: Any means of c
44、onnecting ports other than a single cableassembly3.1.6 frame: A sequence of 4 or more data characters surrounded by FLAG characters.3.1.7 Line: The pair of balanced electrical conductors connecting (1) the positive side of the linedriver port connector to the positive side of the line receiver port
45、connector and (2) thenegative side of the line driver port connector to the negative side of the line receiver portconnector.3.1.8 Line+: The line conductor connecting the positive side of the line driver port connector to thepositive side of the line receiver port connector.3.1.9 Line: The line con
46、ductor connecting the negative side of the line driver port connector tothe negative side of the line receiver port connector.3.1.10 Line Driver: The electrical circuitry that set the logical state of the line at the port connector.3.1.11 LineIn+: The line receiver connection to the Line+ conductor.
47、1)Available from American National Standards Institute, 11 West 42nd Street, New York, NY 10036.ANSI X3.293-199643.1.12 LineIn: The line receiver connection to the Line conductor.3.1.13 LineOut+: The line driver connection to the Line+ conductor.3.1.14 LineOut: The line driver connection to the Line
48、 conductor.3.1.15 Line Receiver: The electrical circuitry that detect the logical state of the line at the portconnector including Line Segment Termination. The Line Receiver shall be capable ofreporting bit errors.3.1.16 Line Segment: That portion of a Line between Line Driver and the Line Segment
49、termination.3.1.17 Line Segment termination: The electrical properties of the load on the end of the linesegment opposite the end associated with the Line Driver.3.1.18 Link: The serial connection between ports on two devices including the Line Drivers, LineReceivers, and the associated Cable Assembles.3.1.19 node: A system, controller or device with one or more ports.3.1.20 Port: A line driver and a line receiver operating together on a device (two lines, fourconductors).3.1.21 Port connection: The combination of two lines that tie the line driver in a port to
