1、 REVISIONS LTR DESCRIPTION DATE APPROVED Prepared in accordance with ASME Y14.24 Vendor item drawing REV PAGE REV PAGE REV STATUS OF PAGES REV PAGE 1 2 3 4 5 6 7 8 9 10 11 12 PMIC N/A PREPARED BY Phu H. Nguyen DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 http:/www.landandmaritime.dla.mil/ Origina
2、l date of drawing YY MM DD CHECKED BY Phu H. Nguyen TITLE MICROCIRCUIT, LINEAR, SINGLE CHANNEL HIGH SPEED, LOW SIDE GATE DRIVER (WITH 4-A PEAK SOURCE AND 8-A PEAK SINK), MONOLITHIC SILICON 13-06-06 APPROVED BY Thomas M. Hess SIZE A CODE IDENT. NO. 16236 DWG NO. V62/13608 REV PAGE 1 OF 12 AMSC N/A 59
3、62-V065-13 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/13608 REV PAGE 2 1. SCOPE 1.1 Scope. This drawing documents the general requirements of a high performance single
4、channel high-speed, low side gat driver (with 4-A peak source and 8-A peak sink) microcircuit, with an operating temperature range of -55C to +125C. 1.2 Vendor Item Drawing Administrative Control Number. The manufacturers PIN is the item of identification. The vendor item drawing establishes an admi
5、nistrative control number for identifying the item on the engineering documentation: V62/13608 - 01 X E Drawing Device type Case outline Lead finish number (See 1.2.1) (See 1.2.2) (See 1.2.3) 1.2.1 Device type(s). Device type Generic Circuit function 01 UCC27512-EP Single channel high-speed, low sid
6、e gat driver (with 4-A peak source and 8-A peak sink) 1.2.2 Case outline(s). The case outlines are as specified herein. Outline letter Number of pins Package style X 6 Small Outline No-Lead 1.2.3 Lead finishes. The lead finishes are as specified below or other lead finishes as provided by the device
7、 manufacturer: Finish designator Material A Hot solder dip B Tin-lead plate C Gold plate D Palladium E Gold flash palladium Z Other Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG N
8、O. V62/13608 REV PAGE 3 1.3 Absolute maximum ratings. 1/ 2/ 3/ Supply voltage range, (VDD) . -0.3 V to 20 V OUT voltage DC . -0.3 V to VDD+ 0.3 V Repetitive pulse less than 200 ns . -2.0 V to VDD+0.3 V 4/ Maximum output continuous current (OUTH source current and OUTL sink current): IOUT_DC(source)
9、0.3 A IOUT_DC(sink) 0.6 A Maximum output pulse current (0.5 s) (OUTH source current and OUTL sink current): IOUT_pulsed(source) 4 A IOUT_pulsed(sink) . 8 A IN+, IN- . -0.3 V to 20 V 5/ ESD: Human Body Model, HBM . 4000 V Charged Device Model, CDM . 1000 V Junction temperature range, TJ-55C to 150C S
10、torage temperature range -65C to 150C Lead temperature: Soldering, 10 sec 300C Reflow . 260C 1.4 Recommended operating conditions. 6/ Supply voltage range, (VDD) . 4.5 V to 18 V Operating junction temperature range -55C to 125C Input voltage, IN+ and IN- 0 V to 18 V _ 1/ Stresses beyond those listed
11、 under “absolute maximum rating” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditi
12、ons for extended periods may affect device reliability. 2/ All voltages are with respect to GND unless otherwise noted. Currents are positive into, negative out of the specified terminal. See Packaging Section of the manufacturer datasheet for thermal limitations and considerations of packages. 3/ T
13、hese devices are sensitive to electrostatic discharge; follow proper device handling procedures. 4/ Values are verified by characterization on bench. 5/ Maximum voltage on input pins is not restricted by the voltage on the VDDpin. 6/ Use of this product beyond the manufacturers design rules or state
14、d parameters is done at the users risk. The manufacturer and/or distributor maintain no responsibility or liability for product used beyond the stated limits. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A
15、 CODE IDENT NO. 16236 DWG NO. V62/13608 REV PAGE 4 1.5 Thermal characteristics. Thermal metric 7/ Case outline X Units Junction to ambient thermal resistance, JA8/ 85.6 C/W Junction to case (top) thermal resistance, JCtop9/ 100.1 Junction to board thermal resistance, JB10/ 58.6 Junction to top chara
16、cterization parameter, JT11/ 7.5 Junction to board characterization parameter, JB12/ 58.7 Junction to case (bottom) thermal resistance, JCbot13/ 23.7 2. APPLICABLE DOCUMENTS JEDEC SOLID STATE TECHNOLOGY ASSOCIATION (JEDEC) JESD51-2a Integrated Circuits Thermal Test Method Environment Conditions Natu
17、ral Convection (Still Air) JESD51-7 High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages JESD51-8 Integrated Circuits Thermal Test Method Environment Conditions Junction-to-board (Copies of these documents are available online at http:/www.jedec.org or from JEDEC Solid St
18、ate Technology Association, 3103 North 10th Street, Suite 240S, Arlington, VA 22201-2107). AMERICAN NATIONAL STANDARDS INSTITUTE (ANSI) STANDARD ANSI SEMI STANDARD G30-88 null Test Method for Junction-to-Case Thermal Resistance Measurements for Ceramic Packages (Applications for copies should be add
19、ressed to the American National Standards Institute, Semiconductor Equipment and Materials International, 1819 L Street, NW, 6 th floor, Washington, DC 20036 or online at http:/www.ansi.org). 7/ For more information about traditional and new thermal metrics, see manufacturer data. 8/ The junction to
20、 ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K-board, as specified in JESD51-7, in an environment described in JESD51-2a. 9/ The junction to case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No
21、specified JEDEC- standard test exists, but a close description can be found in the ANSI SEMI standard G30-88. 10/ The junction to board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB temperature, as described in JESD51-8. 11/ The junc
22、tion to top characterization parameter, JT, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining JA, using a procedure described in JESD51-2a (sections 6 and 7). 12/ The junction to board characterization parameter, JB, estimates the
23、 junction temperature of a device in a real system and is extracted from the simulation data for obtaining JA, using a procedure described in JESD51-2a (sections 6 and 7). 13/ The junction to case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No
24、specified JEDEC- standard test exists, but a close description can be found in the ANSI SEMI standard G30-88 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/13608 REV PAGE 5
25、 3. REQUIREMENTS 3.1 Marking. Parts shall be permanently and legibly marked with the manufacturers part number as shown in 6.3 herein and as follows: A. Manufacturers name, CAGE code, or logo B. Pin 1 identifier C. ESDS identification (optional) 3.2 Unit container. The unit container shall be marked
26、 with the manufacturers part number and with items A and C (if applicable) above. 3.3 Electrical characteristics. The maximum and recommended operating conditions and electrical performance characteristics are as specified in 1.3, 1.4, and table I herein. 3.4 Design, construction, and physical dimen
27、sion. The design, construction, and physical dimensions are as specified herein. 3.5 Diagrams. 3.5.1 Case outline. The case outline shall be as shown in 1.2.2 and figure 1. 3.5.2 Terminal connections. The terminal connections shall be as shown in figure 2. 3.5.3 Terminal function. The terminal funct
28、ion shall be as shown in figure 3. 3.5.4 Device logic table. The device logic table shall be as shown in figure 4. 3.5.5 Functional block diagram. The functional block diagram shall be as shown in figure 5. 3.5.6 Non-Inverting configuration. The Non-Inverting configuration shall be as shown in figur
29、e 6. 3.5.7 Inverting configuration. The Inverting configuration shall be as shown in figure 7. 3.5.8 Enable and disable function using IN+ pin. The Enable and disable function using IN+ pin shall be as shown in figure 8. 3.5.9 Enable and disable function using IN- pin. The Enable and disable functio
30、n using IN- pin shall be as shown in figure 9. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/13608 REV PAGE 6 TABLE I. Electrical performance characteristics. 1/ Test Symb
31、ol Test conditions 2/ Limits Unit Min Typ Max Bias current Startup current IDD(off)VDD = 3.4 V IN+ = VDD, IN- = GND 40 100 145 A IN+ = IN- = GND or IN+ = IN- = VDD 25 75 138 IN+ = VDD, IN- = GND 20 60 110 Under Voltage Lockout (UVLO) Supply start threshold VON3.70 4.20 4.65 V Minimum operating volta
32、ge after supply start VOFF3.45 3.9 4.35 Supply voltage hysteresis VDD_H0.2 0.3 0.5 Inputs (IN+, IN-) Input signal high threshold VIN_HOutput high for IN+ pin, Output low for IN- pin 2.2 2.4 V Input signal low threshold VIN_LOutput low for IN+ pin, Output high for IN- pin 1.0 1.2 Input signal hystere
33、sis VIN_HYS1.0 Source/Sink current Source/sink peak current 3/ ISRC/SNK CLOAD = 0.22 F, FSW = 1 kHz -4/+8 A Outputs (OUTH, OUTL, OUT) High output voltage VDD-VOHVDD= 12 V, IOUTH= -10 mA 50 80 mV VDD= 4.5 V, IOUTH= -10 mA 60 125 Low output voltage VOLVDD= 12 V, IOUTL= 10 mA 5 6 VDD= 4.5 V, IOUTL= 10
34、mA 5.5 9 Output pull-up resistance 4/ ROHVDD= 12 V, IOUTH= -10 mA 5.0 7.5 VDD= 4.5 V, IOUTH= -10 mA 5.0 10.0 Output pull-down resistance ROLVDD= 12 V, IOUTL= 10 mA 0.375 0.650 VDD= 4.5 V, IOUTL= 10 mA 0.45 0.750 Switching time See FIGURE 6-9 Rise time tRVDD= 12 V, CLOAD= 1.8 nF, connect to OUTH and
35、OUTL pins tied together 8 12 ns VDD= 4.5 V, CLOAD= 1.8 nF, 16 22 Fall time tFVDD= 12 V, CLOAD= 1.8 nF, connect to OUTH and OUTL pins tied together 7 11 VDD= 4.5 V, CLOAD= 1.8 nF, 7 11 IN+ to output propagation delay tD1VDD= 12 V, 5-V input pulse CLOAD= 1.8 nF, connect to OUTH and OUTL pins tied toge
36、ther 4 13 23 VDD= 4.5 V, 5-V input pulse CLOAD= 1.8 nF, connect to OUTH and OUTL pins tied together 4 15 26 IN- to output propagation delay tD2VDD= 12 V, CLOAD= 1.8 nF, connect to OUTH and OUTL pins tied together 4 13 23 VDD= 4.5 V, CLOAD= 1.8 nF, connect to OUTH and OUTL pins tied together 4 19 30
37、1/ Testing and other quality control techniques are used to the extent deemed necessary to assure product performance over the specified temperature range. Product may not necessarily be tested across the full temperature range and all parameters may not necessarily be tested. In the absence of spec
38、ific parametric testing, product performance is assured by characterization and/or design. 2/ VDD= 12 V, TA= TJ = -55C to 125C, 1-F capacitor from VDDto GND. Currents are positive into, negative out of the specified terminal. 3/ Ensure by design. 4/ ROH represents on-resistance of P-Channel MOSFET i
39、n pull-up structure of the device output stage. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/13608 REV PAGE 7 Case X Dimensions Symbol Millimeters Symbol Millimeters Min
40、Max Min Max A 0.70 0.80 b1 0.45 0.55 A1 0.20 TYP D/E 2.85 3.15 A2 0.00 0.05 e 0.95 BSC b 0.30 0.40 NOTES: 1. All linear dimensions are in millimeters. 2. This drawing is subject to change without notice. 3. SON (Small Outline No-Lead) package configuration. 4. The package thermal pad must be soldere
41、d to the board for thermal and mechanical performance. 5. See the additional figure in the manufacturers data for details regarding the exposed thermal pad features and dimensions. FIGURE 1. Case outline. AA2A1D/EPIN 1 INDEX AREATOP AND BOTTOM1 36 4b16 PLSb6 PLSeTHERMAL PAD1 36 4Provided by IHSNot f
42、or ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/13608 REV PAGE 8 Case outline X Terminal number Terminal symbol Terminal number Terminal symbol 1 IN+ 6 IN- 2 GND 5 GND 3 VDD 4 OUT FIGURE 2. Ter
43、minal connections. Terminal I/O Function Number Name 1 IN- I Non-inverting input: When the driver is used in inverting configuration connect IN+ to VDD in order to enable output, OUT held LOW if IN+ is unbiased or floating. 2, 5 GND - Ground: All signals referenced to this pin. It is recommended to
44、connect pin 2 and pin 5 on PCB as close to the device as possible. 3 VDD I Bias supply input 4 OUTIN- O Sourcing/sinking current output of driver. 6 I Inverting input: When the driver is used in non-inverting configuration connect IN- to GND in order to enable output, OUT held LOW if IN- is unbiased
45、 or floating. FIGURE 3. Terminal function. IN+ IN- OUTH OUTL OUT L L High impedance L L L H High impedance L L H L H High impedance H H H High impedance L L x 1/ Any High impedance L L Any x 1/ High impedance L L FIGURE 4. Device Logic table. Provided by IHSNot for ResaleNo reproduction or networkin
46、g permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/13608 REV PAGE 9 FIGURE 5. Functional block diagram. NOTE: (PWM input to IN+ pin (IN- pin tied to GND), Output represents OUTH and OUTL pins tied together) FIGURE 6. Non-inverting co
47、nfiguration. VDDVDDUVLOVDD230 k200 kVDDOUTGNDIN+IN-GNDIN-PINOUTPUTINPUT(IN+PIN)HIGHLOW90%10%trtD1trtD1HIGHLOWProvided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/13608 REV PAGE 1
48、0 NOTE: (PWM input to IN- pin (IN+ pin tied to VDD), Output represents OUTH and OUTL pins tied together) FIGURE 7. Inverting configuration. NOTE: (Enable and disable signal applied to IN+ pin, PWM input to IN- pin, Output represents OUTH and OUTL pins tied together) FIGURE 8. Enable and Disable function using IN+ pin. IN+PINOUTPUTINPUT(IN-PIN)HIGHLOW90
