1、 REVISIONS LTR DESCRIPTION DATE APPROVED Prepared in accordance with ASME Y14.24 Vendor item drawing REV PAGE 84 85 REV PAGE 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 REV PAGE 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 REV PAGE 18 19 20 21 22 23 24 25 2
2、6 27 28 29 30 31 32 33 34 35 36 37 38 39 REV STATUS OF PAGES REV PAGE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 PMIC N/A PREPARED BY Phu H. Nguyen DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 http:/www.landandmaritime.dla.mil/ Original date of drawing YY-MM-DD CHECKED BY Phu H. Nguyen TITLE MICRO
3、CIRCUIT, DIGITAL SIGNAL PROCESSOR, MONOLITHIC SILICON 13-08-13 APPROVED BY Thomas M. Hess SIZE A CODE IDENT. NO. 16236 DWG NO. V62/12605 REV PAGE 1 OF 85 AMSC N/A 5962-V072-13 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLU
4、MBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/12605 REV PAGE 2 1.1 Scope. This drawing documents the general requirements of a high performance digital processor microcircuit, with an operating temperature range of -55C to +125C. 1.2 Vendor Item Drawing Administrative Control Number. The manufa
5、cturers PIN is the item of identification. The vendor item drawing establishes an administrative control number for identifying the item on the engineering documentation: V62/12605 - 01 X E Drawing Device type Case outline Lead finish number (See 1.2.1) (See 1.2.2) (See 1.2.3) 1.2.1 Device type(s).
6、Device type Generic Circuit function 01 OMAPL138B-EP Digital signal processor 1.2.2 Case outline(s). The case outline(s) are as specified herein. Outline letter Number of pins JEDEC PUB 95 Package style X 361 JEDEC MO-275 Plastic ball grid array 1.2.3 Lead finishes. The lead finishes are as specifie
7、d below or other lead finishes as provided by the device manufacturer: Finish designator Material A Hot solder dip B Tin-lead plate C Gold plate D Palladium E Gold flash palladium Z Other Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND M
8、ARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/12605 REV PAGE 3 1.3 Absolute maximum ratings. 1/ Supply voltage range: Core logic, variable and fixed (CVDD, RVDD, RTC_CVDD, PLL0_VDDA, PLL1_VDDA, SATA_VDD, USB_CVDD) . -0.5 V to 1.4 V 2/ I/O, 1.8 V (USB0_VDDA18, USB1_VDDA18, SATA_VDDR,
9、 DDR_DVDD18) . -0.5 V to 2.0 V 2/ I/O, 3.3 V (DVDD3318_A, DVDD3318_B, DVDD3318_C, USB0_VDDA33, USB1_VDDA33) . -0.5 V to 3.8 V 2/ Input voltage ranges (VI): Oscillator inputs (OSCIN, RTC_XI), 1.2 V . -0.3 V to CVDD+ 0.3 V Dual voltage LVCMOS inputs 3.3 V or 1.8 V (steady state) -0.3 V to DVDD+ 0.3 V
10、Dual voltage LVCMOS inputs, operated at 3.3 V (Transient) DVDD+ 20% up to 20% of signal period Dual voltage LVCMOS inputs, operated at 1.8 V (transient) . DVDD+ 30% up to 30% of signal period USB 5V tolerant IOs: (USB0_DM, USB0_DP, USB0_ID, USB1_DM, USB1_DP) . 5.25 v 3/ USB0 VBUS Pin 5.50 V 3/ Outpu
11、t voltage ranges, (VO): Dual voltage LVCMOS outputs, 3.3 V or 1.8 V (steady state) . -0.5 V to DVDD+ 0.3 V Dual voltage LVCMOS outputs, operated at 3.3 V (Transient) DVDD+ 20% up to 20% of signal period Dual voltage LVCMOS outputs, operated at 1.8 V (Transient) DVDD+ 30% up to 30% of signal period C
12、lamp current, Input or output voltages 0.3 V above or below their respective power rails. Limits clamp current that flows through the I/Os internal diode protection cells. 20 mA Operating Junction temperature ranges, (TJ) -55C to 125C Storage temperature range (TSTG) . -55C to 150C ESD stress voltag
13、e, (VESD) 4/ : Human Body Level (HBL) 5/ . 1000 V Charged Device Model (CDM) 6/ . 500 V 1/ Stresses beyond those listed under “absolute maximum rating” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions bey
14、ond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2/ Alll voltage value with respect to VSS, USB0_VSSA33, USB_VSSA, PLL0_VSSA, OSCVSS, RTC_VSS. 3/ Up to maximum of 24 hours. 4
15、/ Electronic discharge (ESD) to measure device sensitivity/immunity to damage caused by electrostatic dischargers into the device. 5/ Level listed above is the passing level per ANSI/JEDEC JS-001-2010. JEDEC document JEP 155 states that 500 V HBM allows safe manufacturing with a standard ESD control
16、 process, and manufacturing with less than 500 V HBM is possible if necessary precaution are taken. Pin listed as 1000 V may actually have higher performance. 6/ Level listed above is the passing level per EIA-JEDEC JESD22-C101E. JEDEC document JEP 155 states that 250 V CDM allows safe manufacturing
17、 with a standard ESD control process. Pin listed as 250 V may actually have higher performance. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/12605 REV PAGE 4 1.4 Recommen
18、ded operating conditions. 7/ Name Description Condition Min Max Unit Supply Voltage CVDD Core logic supply voltage (variable) 1.3 V operating point 1.25 1.35 V 1.2 V operating point 1.14 1.32 1.1 V operating point 1.05 1.16 1.0 V operating point 0.95 1.05 RVDD Internal RAM supply voltage 456 MHz ver
19、sion 1.25 1.35 V 375 MHz version 1.14 1.32 RTC_CVDD 8/ RTC core logic supply voltage 0.9 1.32 V PLL0_VDDA PLL0 supply voltage 1.14 1.32 PLL1_VDDA PLL1 supply voltage 1.14 1.32 SATA_VDD SATA core logic supply voltage 1.14 1.32 USB_CVDD USB0, USB1 core logic supply voltage 1.14 1.32 USB0_VDDA18 USB0 P
20、HY supply voltage 1.71 1.89 USB0_VDDA33 USB0 PHY supply voltage 3.15 3.45 USB1_VDDA18 USB1 PHY supply voltage 1.71 1.89 USB1_VDDA33 USB1 PHY supply voltage 3.15 3.45 DVDD18 9/ 1.8 V logic supply 1.71 1.89 SATA_VDDR SATA PHY internal regular supply voltage 1.71 1.89 DDR_DVDD18 9/ DDR2 PHY supply volt
21、age 1.71 1.89 DDR_VREF DDR2/mDDR reference voltage 0.49* 10/ 0.51* 10/ DDR_ZP DDR2/mDDR impedance control, connect via 50 resistor to VSSVSSTYP DVDD3318_A Power group A dual voltage IO supply voltage 1.8 V operating point 1.71 1.89 3.3 V operating point 3.15 3.45 DVDD3318_B Power group B dual voltag
22、e IO supply voltage 1.8 V operating point 1.71 1.89 3.3 V operating point 3.15 3.45 DVDD3318_C Power group C dual voltage IO supply voltage 1.8 V operating point 1.71 1.89 3.3 V operating point 3.15 3.45 Supply Ground VSS Core logic digital ground 0 0 V PLL0_VSSA PLL0 ground PLL1_VSSA PLL1 ground SA
23、TA_VSS SATA PHY ground OSCVSS 11/ Oscillator ground RTC_VSS 11/ RTC Oscillator ground USB0_VSSA USB0 PHY ground USB0_VSSA33 USB0 PHY ground Voltage input high VIH High level input voltage, Dual voltage I/O 3.3 V 12/ 2 V High level input voltage, Dual voltage I/O 1.8 V 12/ 0.65*DVDD High level input
24、voltage, RTC_XI 0.8*RTC_CVDD High level input voltage, OSCIN 0.8*CVDD See foot note at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/12605 REV PAGE 5 1.4 Rec
25、ommended operating conditions - Continued. 7/ Name Description Condition Min Max Unit Voltage input low VIL Low level input voltage, Dual voltage I/O 3.3 V 12/ 0.8 V Low level input voltage, Dual voltage I/O 1.8 V 12 0.35*DVDD Low level input voltage, RTC_XI 0.2*RTC_CVDD Low level input voltage, OSC
26、IN 0.2*CVDD USB USB0_VBUS USB external charge pump input 0 5.25 V Differential Clock input Voltage Differential input voltage, SATA_REFCLKP and SATA_REFCLKN250 2000 mV Transition time ttTransition time, 10%-90%, All inputs (unless otherwise specified in the electrical data section) 0.25P or 10 13/ n
27、s Military temperature grade (M suffix) CVDD = 1.2 V operating point 0 345 14/ 7/ Use of this product beyond the manufacturers design rules or stated parameters is done at the users risk. The manufacturer and/or distributor maintain no responsibility or liability for product used beyond the stated l
28、imits. 8/ The RTC provides an option for isolating the RTC_CVDD from the CVDD to reduce current leakage when the RTC is powered independently. If these power supply are not isolated (CTRL.SPLITPOWER =0), RTC_CVDD must be equal to or greater than CVDD. 9/ DVDD18 must be powered even if all of the DVD
29、D3318_x supplies are operated at 3.3 V. 10/ DDR_DVDD18 11/ When an external crystal is used oscillator (OSC_VSS, RTC_VSS) ground must be kept separate from other grouns and connected directly to the crystal load capacitor ground. These pins are shorted to VSS on the device itself and should not be c
30、onnected to VSS on the circuit board. If a crystal is not used and the clock input is driven directly, then the oscillator VSS may be connected to board ground. 12/ These IO specifications apply to the dual voltage IOs only and do not apply to DDR2/mDDR or SATA interfaces. DDR2/mDDR IOs are 1.8 V IO
31、s and adhere to the JESD79-2A standard. 13/ Whichever is smaller. P = the period of the applied signal. Maintaining transition times as fast as possible is recommended to improve noise immunity on input signals. 14/ The operating point is 300 MHz on revision 1.x silicon. Provided by IHSNot for Resal
32、eNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/12605 REV PAGE 6 1.4 Recommended operating conditions - Continued. 7/ Thermal resistance characteristics for case outline X: No. C/W 15/ Air Flow (m/s) 1
33、6/ 1 Junction to case, (RJC) 7.3 N/A 2 Junction to case, (RJC) 12.4 N/A 3 Junction to case, (RJC) 23.7 0.0 4 Junction to moving air, (RJMA) 21.0 0.5 5 20.1 1.0 6 19.3 2.0 7 18.4 4.0 8 Junction to package top, (PsiJT) 0.2 0.0 9 0.3 0.5 10 0.3 1.0 11 0.4 2.0 12 0.5 4.0 13 Junction to board, (PsiJB) 12
34、.3 0.0 14 12.2 0.5 15 12.1 1.0 16 12.0 2.0 17 11.9 4.0 1.5 Recommended Power On Hours (POH). Silicon Revision Speed Grade Operating Junction Temperature (TJ) Nominal CVDD voltage (V) Power On Hour POH (hours) B 345 MHz 0 to 105C 1.2 V 100,000 B 345 MHz -55 to 125C 1.2 V 29,145 15/ These measurements
35、 were conducted in s JEDEC defined as 2S2P system and will change based on environment as well as application. For more information see these EIA/JEDEC standards JESD51-2 and JESD51-7. Power dissipation of 1 W and ambient temp of 70C assumed. PCB with 2 oz (70 m) top and bottom copper thickness and
36、1.5 oz (50 m) inner copper thickness. 16/ m/s = meters per second. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/12605 REV PAGE 7 2. APPLICABLE DOCUMENTS JEDEC SOLID STATE
37、 TECHNOLOGY ASSOCIATION (JEDEC) JEP95 Registered and Standard Outlines for Semiconductor Devices JEP 155 Recommended ESD target levels for HBM/MM qualification JESD51-2 Integrated Circuits thermal test method environmental conditions Natural convection (Still Air) JESD51-7 High Effective Thermal Con
38、ductivity Test Board for Leaded Surface Mount Package. JESD22 Electro Static Discharge (ESD) protection JESD79-2A DDR2 SDRAM standard (Copies of these documents are available online at http:/www.jedec.org or from JEDEC Solid State Technology Association, 3103 North 10th Street, Suite 240S, Arlington
39、, VA 22201.) 3. REQUIREMENTS 3.1 Marking. Parts shall be permanently and legibly marked with the manufacturers part number as shown in 6.3 herein and as follows: A. Manufacturers name, CAGE code, or logo B. Pin 1 identifier C. ESDS identification (optional) 3.2 Unit container. The unit container sha
40、ll be marked with the manufacturers part number and with items A and C (if applicable) above. 3.3 Electrical characteristics. The maximum and recommended operating conditions and electrical performance characteristics are as specified in 1.3, 1.4, and table I herein. 3.4 Design, construction, and ph
41、ysical dimension. The design, construction, and physical dimensions are as specified herein. 3.5 Diagrams. 3.5.1 Case outline(s). The case outline(s) shall be as shown in 1.2.2 and figure 1. 3.5.2 Terminal connections. The terminal connections shall be as shown in figure 2. 3.5.3 Functional block di
42、agram. The functional block diagram shall be as shown in figure 3. 3.5.4 Test load circuit for AC timing measurements. The test load circuit for AC timing measurements shall be as shown in figure 4. 3.5.5 Input and Output voltage reference levels for AC timing measurements. The Input and Output volt
43、age reference levels for AC timing measurements shall be as shown in figure 5. 3.5.6 Rise and Fall transaction time voltage reference levels. The Rise and Fall transaction time voltage reference levels shall be as shown in figure 6. 3.5.7 Power ON reset timing. The Power ON rest timing shall be as s
44、hown in figure 7. 3.5.8 Warm Reset timing. The Warm Reset timing shall be as shown in figure 8. 3.5.9 On chip oscillator. The on chip oscillator shall be as shown in figure 9 3.5.10 External 1.2 V clock source. The external 1.2 V clock source shall be as shown in figure 10. Provided by IHSNot for Re
45、saleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/12605 REV PAGE 8 3.5.11 EMIFA basic SDRAM Write operation. The EMIFA basic SDRAM Write operation shall be as shown in figure 11. 3.5.12 EMIFA basic SD
46、RAM Read operation. The EMIFA basic SDRAM Read operation shall be as shown in figure 12. 3.5.13 Asynchronous Memory Read timing for EMIFA. The asynchronous Memory Read timing for EMIFA shall be as shown in figure 13. 3.5.14 Asynchronous Memory Write timing for EMIFA. The asynchronous Memory Write ti
47、ming for EMIFA shall be as shown in figure 14. 3.5.15 EMA_WAIT Read timing requirements. The EMA_WAIT Read timing requirements shall be as shown in figure 15. 3.5.16 EMA_WAIT Write timing requirements. The EMA_WAIT Write timing requirements shall be as shown in figure 16. 3.5.17 MMC/SD Host command
48、timing. The MMC/SD Host command timing shall be as shown in figure 17. 3.5.18 MMC/SD Card response timing. The MMC/SD Card response timing shall be as shown in figure 18. 3.5.19 MMC/SD Host Write timing. The MMC/SD Host Write timing shall be as shown in figure 19. 3.5.20 MMC/SD Host Read and Card Status timing. The MMC/SD Host Read and Card Status timing shall be as shown in figure 20. 3.5.21 McASP Block Diagr
