1、 ECMA Standard-342February 2003Standardizing Information and Communication SystemsPhone: +41 22 849.60.00 - Fax: +41 22 849.60.01 - URL:http:/www.ecma.ch - Internet: helpdeskecma.chRapidIOTMInterconnectSpecificationInternational ECMA Standard-342February 2003Standardizing Information and Communicati
2、on SystemsPhone: +41 22 849.60.00 - Fax: +41 22 849.60.01 - URL:http:/www.ecma.ch - Internet: helpdeskecma.chRapidIOTMInterconnect SpecificationRapidIOTMInterconnectSpecificationInternational Brief HistoryThe RapidIO architecture was developed to address the need for a high-performance low pin count
3、 packet-switched system levelinterconnect to be used in a variety of applications as an open standard. The architecture is targeted toward networking, telecom, andhigh performance embedded applications. It is intended primarily as an intra-system interface, allowing chip-to-chip and board-to-board c
4、ommunications at Gigabyte per second performance levels. It provides a rich variety of features including high data band-width, low-latency capability and support for high-performance I/O devices, as well as providing globally shared memory, messagepassing, and software managed programming models. I
5、n its simplest form, the interface can be implemented in a FPGA end point.The interconnect defines a protocol independent of a physical implementation. The physical features of an implementation utilizingthe interconnect are defined by the requirements of the implementation, such as I/O signaling le
6、vels, interconnect topology, physicallayer protocol, error detection, and so forth. The architecture is intended and partitioned to allow adaptation to a multitude of applica-tions.This ECMA Standard has been adopted by the General Assembly in February 2003.Overview of the standardThis overview expl
7、ains each of the three layers of the RapidIO architecture, their interrelationships, an the system and device inter-operability:1. Logical layerThe logical layer defines the overall protocol and packet formats, the types of transactions that can be carried out with RapidIO, how addressing is handled
8、. The logical specifications are partitioned into two partitions: Partition I: Input/Output Logical Specification Partition II: Message Passing Logical Specification Partition V: Globally Shared Memory Logical Specification2. Transport layerThe transport layer provides the necessary route informatio
9、n for a packet to move from one point to another. This information is covered in Partition III: Common Transport Specification.3. Physical layerThe physical layer contains the device level interface such as packet transport mechanisms, flow control, electrical characteristics, and low-level error ma
10、nagement. This standard covers these topics in Partition IV: Physical 8/16 LP-LVDS Specification, and in Partition VI: Physial Layer 1X/4X LP-Serial Specification.4. Inter-operability This consists of a standard setod device and system design solutions to provide for interoperability. The specificat
11、ion is given in Patition VII: Inter-operability Specification System and Device.NOTERapidIO specifications are structured so that additions can be made to each without affecting the others. For example, each logi-cal specification is independent and can be implemented alone.Partitions I, II and V: L
12、ogical SpecificationsIn RapidIO, the logical layer is subdivided into two specifications that support distributed I/O processing. Partition I: Input/Output Logical Specification explains how RapidIO supports input-output systems and Partition II: Message Passing Logi-cal Specification describes the
13、message passing features of the RapidIO interconnect. Additionally, Partition V: GloballyShared Memory Logical Specification, specifies an extension for applications that support cache-coherency and multi-processing.The logical specifications do not imply a specific transport or physical interface,
14、therefore they are specified in a bit streamformat. Necessary bits are added to the logical encodings for each lower layer in the hierarchy.Because all logical layers fulfill the same data communication functions no matter what programming model they support,specifications written to this logical le
15、vel address similar issues. In RapidIO, this similarity among the logical specificationsis reflected in the chapter contents, with each of the logical specifications containing the following chapters: Chapter 1, “ System Models,” provides explanations and figures of the types of systems that can use
16、 a RapidIO interface. Chapter 2, “Operation Descriptions,” describes the sets of operations and transactions supported by RapidIO message passing and input/output protocols. Chapter 3, “Packet Format Descriptions,” breaks down packets into the two basic classes of request and response packets and th
17、en discusses and illustrates the format types within each class for each logical specification. Chapter 4, “Message Passing Registers,” and Chapter 4, “Input/Output Registers,” provides a memory map of registers used in the message passing and I/O specifications, and then subsections that discuss an
18、d illustrate each register.The message passing logical specification has an annex added that describes in greater detail two examples of RapidIO mes-sage passing models, one a simple model and one a more extended model.The extension to the logical specifications as given in Partition V contains the
19、following chapters: Chapter 1, “Overview,” describes the set of operations and transactions supported by the RapidIO globally shared memory protocols. Chapter 2, “System Models,” introduces some possible devices that could participate in a RapidIO GSM system environment. The chapter explains the mem
20、ory directory-based mechanism that tracks memory accesses and maintains cache coherence. Transaction ordering and deadlock prevention are also covered. Chapter 3, “Operation Descriptions,” describes the set of operations and transactions supported by the RapidIO globally-shared memory (GSM) protocol
21、s. Chapter 4, “Packet Format Descriptions,” contains the packet format definitions for the GSM specification. The two basic types, request and response packets, with their sub-types and fields are defined. The chapter explains how memory read latency is handled by RapidIO. Chapter 5, “Globally Share
22、d Memory Registers,” describes the visible register set that allows an external processing element to determine the globally shared memory capabilities, configuration, and status of a processing element using this logical specification. Only registers or register bits specific to the GSM logical spe
23、cification are explained. Refer to the other RapidIO logical, transport, and physical specifications of interest to determine a complete list of registers and bit definitions. Chapter 6, “Communication Protocols,” contains the communications protocol definitions for this GSM specification. Chapter 7
24、, “Address Collision Resolution Tables,” explains the actions necessary under the RapidIO GSM model to resolve address collisions. Partition III: Common Transport SpecificationPartition III: Common Transport Specification contains three chapters:The introduction to Partition III: Common Transport Sp
25、ecification offers a general understanding of the features and func-tions of the transport specification. Chapter 1, “Transport Format Description,” describes the routing methods used in RapidIO for sending packets across the systems of switches described in this chapter. Chapter 2, “Common Transpor
26、t Registers,” describes the visible register set that allows an external processing element to determine the capabilities, configuration, and status of a processing element using this RapidIO transport layer definition.Partitions IV and VI: Physical Layer 8/16 LP-LVDS and 1x/4x LP-Serial Specificati
27、onsPartition IV: Physical Layer 8/16 LP-LVDS Specification contains eight chapters and an annex: The introduction to Partition IV: Physical Layer 8/16 LP-LVDS Specification offers a general understanding of the features and functions of the physical layer specification. Chapter 1, “Physical Layer Pr
28、otocol,” describes the physical layer protocol for packet delivery to the RapidIO fabric, including packet transmission, flow control, error management, and link maintenance protocols. Chapter 2, “Packet and Control Symbol Transmission,” defines packet and control symbol delineation and alignment on
29、 the physical port and mechanisms to control the pacing of a packet. Chapter 3, “Control Symbol Formats,” explains the physical layer control formats that manage the packet delivery protocols mentioned in Chapter 2. Chapter 4, “8/16 LP-LVDS Registers,” describes the register set that allows an exter
30、nal processing element to determine the physical capabilities and status of an 8/16 LP-LVDS RapidIO implementation. Chapter 5, “System Clocking Considerations,” discusses the RapidIO synchronous clock and how it is distributed in a typical switch configuration. Chapter 6, “Board Routing Guidelines,”
31、 explains board layout guidelines and application environment considerations for the RapidIO architecture. “Chapter 7,” contains the signal pin descriptions for a RapidIO end point device. Chapter 8, “Electrical Specifications,” describes the low voltage differential signaling (LVDS) electrical spec
32、ifications of the RapidIO 8/16 LP-LVDS device. Annex A, “Interface Management (Informative),” contains information pertinent to interface management in a RapidIO system, including SECDED error tables, error recovery, link initialization, and packet retry state machines. Partition VI: Physical Layer
33、1x/4x LP-Serial Specification containssight chapters and two annexes: Chapter 1, “Overview”, offers a general understanding of the futures of the physical layer specification. Chapter 2, “Packets”, defines the LP-Serial packet format and the fields that are added by the LP-Serial physical layer. Cha
34、pter 3, “Control Symbols”, defines the format of the two classes of control symbols which are the message elements sed by ports connected by an LP-Serial link to manage all aspects of the link operation. Chapter 4, “PCS and PMA Layers”, defines the fonctions provided by the Physical Coding Sublayer
35、(PSC) and the Physical Media Attachment (PMA) sublayer, comprising encoding, link transmission rules, serialization and link initialization. Chapter 5, “LP-Serial Protocol”, defines how packets, control symbols, and the PSC/PMA sublayers are used to implement the physical layer protocol that provide
36、s the reliable delivery of packets between two RapidIO devices that are connected by an LP-Serial link. Chapter 6, “LP-Serial Registers”, defines the physical layer control and status register set. By accessing this LP-Serial Command and Status Register (CSR) set a processing element may query the c
37、apabilities and status, and configure another processing element. Chapter 7, “Signal Descriptions”, describes the signal pin for end point devices and shows the connectivity between processing elements with 1x ports and those with 4x ports. Chapter 8, “A.C. Electrical Specifications”, defines the el
38、ectrical requirements for the LP-Serial device, comprosing two transmission types and three speed grades. Annex A, “Interface Management”, describes state machines showing examples for error recovery, link initialization and packet retry. Annex B, “Bibliography”.Partition VII: Inter-operability Spec
39、ification System and DevicePartition VII: Inter-operability Specification System and Device contains chapters: Chapter 1, “Overview”, provides a short survey about one way of interworking of system components. Chapter 2, “System Exploration and Initialization”, describes a system that is explored an
40、d configured at boot time by processors, in order to support relatively fast-changing plug-and-play or hot-swap systems. Chapter 3, “816 LP-LVDS Device Class Requirements”, describes the requirements for devices adhering to the 8/16 LP-LVDS physical layer specification, and defines three classes of
41、devices with increasing levels of functionality. Chapter 4, “PCI Considerations”, describes architectural considerations for an implementation of a RapidIO to PCI (PVCI 2.2 and PCI x1.0) bridge processing element. Chapter 5, “Globally Shared Memory (GSM) Devices”, defines the portions of the GMS pro
42、tocol necessary to implement different processing elements (devices). Additionally, this chapter contains the 8/16 LP-LVDS and 1x/4x LP-Serial transaction to priority mappings to guarantee that a system maintains cache coherence and is deadlock free.Partition VIII: Error Management Extensions Specif
43、icationPartition VIII: Error Management Extensions Specification contains two chapters and one annex: Chapter 1, “Error Management Extensions”, defines the additional requirements for all physical and logical layers, and describes the behavior of a device when an error is detected and how the new re
44、gisters and bits are managed by sofware and hardware. Chapter 2, “Error Management Registers”, describes the Error Management Extended Features block, and a number of new bits to the existing standard physical layer registers. Annex A provides information and background on the application of the err
45、or management capabilities.ExtensionsExtensions to this base set of RapidIO specifications will be published periodically under separate cover. TerminologyRefer to the Glossary at the back of this document. Conventions| Concatenation, used to indicate that two fields are physically associated as con
46、secutive bitsACTIVE_HIGH Names of active high signals are shown in uppercase text with no overbar. Active-high signals areasserted when high and not asserted when low.ACTIVE_LOW Names of active low signals are shown in uppercase text with an overbar. Active low signals areasserted when low and not a
47、sserted when high. italics Book titles in text are set in italics.REGFIELD Abbreviations or acronyms for registers are shown in uppercase text. Specific bits, fields, or rangesappear in brackets. TRANSACTION Transaction types are expressed in all caps.operation Device operation types are expressed i
48、n plain text. n A decimal value. n-m Used to express a numerical range from n to m. 0bnn A binary value, the number of bits is determined by the number of digits.0xnn A hexadecimal value, the number of bits is determined by the number of digits or from the surroundingcontext; for example, 0xnn may b
49、e a 5, 6, 7, or 8 bit value.- I -SummaryThis summary is intended for anyone who needs a high-level understanding of the RapidIO architecture. The layers of thearchitecture are described, and the functional, physical, and performance features are presented.IntroductionRapidIO is a packet-switched interconnect intended primarily as an intra-system interface for chip-to-chip and board-to-board communications at Gigabyte-per-second performance levels. Uses for the architecture can be found in connectedmicroprocessors, memory, and memor
