1、JEDEC STANDARD DDR4 NVDIMM-N Design Standard (Revision 1.0) JESD248 SEPTEMBER 2016 JEDEC SOLID STATE TECHNOLOGY ASSOCIATION NOTICE JEDEC standards and publications contain material that has been prepared, reviewed, and approved through the JEDEC Board of Directors level and subsequently reviewed and
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9、South Arlington, VA 22201-2107 or refer to www.jedec.org under Standards-Documents/Copyright Information. JEDEC Standard No. 248 Page 1 Revision 1.0 DDR4 NVDIMM-N Design Standard (Revision 1.0) (From JEDEC Board Ballot JCB-16-28, formulated under the cognizance of the JC-45.6 Subcommittee on Hybrid
10、Modules.) Scope 1This standard defines the electrical and mechanical requirements for 288-pin, 1.2 Volt (VDD), Double Data Rate, Synchronous SDRAM Non-Volatile Dual In-Line Memory Modules with NAND Flash backup (DDR4 NVDIMM-N). A DDR4 NVDIMM-N is a Hybrid Memory Module with a DDR4 DIMM interface con
11、sisting of DRAM that is made non-volatile through the use of NAND Flash. NVDIMM-N modules adhere to the Byte Addressable Energy Backed Interface Standard, JESD245, that provides detailed logical behavior, interface, and register definitions. These DDR4 NVDIMM-N modules are intended for use as main m
12、emory or storage when installed in PCs. System interface constraints are included which provide an initial basis for DDR4 NVDIMM-N and LR NVDIMM-N designs. Modifications to these constraints may be required to meet all system timing, signal integrity and thermal requirements for PC4-1600, PC4-1866,
13、PC4-2133, PC4-2400, PC4-2666 and PC4-3200 support. All DDR4 NVDIMM-N implementations must use simulations and lab verification to ensure proper timing requirements and signal integrity in the design. An additional lower voltage of TBD is defined. PC4L is used to reference DIMMs capable of operation
14、at this voltage level. The annex for each raw card will have specific entries to indicate DIMM operation at PC4 and PC4L voltage levels. This standard follows the JEDEC standard DDR4 component standard (refer to JEDEC standard JESD79-4, at www.jedec.org). Table 1 DDR4 Product Family Attributes DIMM
15、Organization x72 ECC Notes DIMM Dimensions (nominal) 133.35 mm x 31.25 mm Refer to MO-309 133.35 mm x 18.75 mm Refer to MO-309 Pin Count 288 DDR4 SDRAMs Supported 4Gb, 8Gb, 16Gb 78/106-ball FBGA package for x4 and x8 devices. Refer to MO-207: variations DT-z, DW-z Capacity 4GB, 8GB, 16GB, 32GB, 64GB
16、, 128GB SDRAM width x4, x8 Serial Presence Detect, Thermal Sensor (SPD-TSE) 512 byte TSE2004av specifications Voltage Options VDD: PC4 - 1.2 Volt 5%, PC4L - TBD VPP: 2.5 Volt +10%, -5% The VPP supply has VSS as its return path. VPP is a separate supply, VDDSPD. VDDSPD: 2.5 Volt 10% The VDDSPD supply
17、 has VSS as its return path. VDDSPD is separate from the VPP power plane. VDDSPD is shared between the SPD-TSE and the RCD (register). The RCD only supports 2.5V. V_12: +12 Volt 15% The +12 V supply has VSS as its return path. +12 V is required for NVDIMM-N operation. Interface 1.2 V signaling JEDEC
18、 Standard No. 248 Page 2 Revision 1.0 Environmental Requirements 2288-pin Registered DDR4 NVDIMM-N modules are intended for use in a variety of environments including standard office environments that have limited capacity for heating and air conditioning. Table 2 Environmental Parameters Symbol Par
19、ameter Rating Units Notes TOPR Operating Temperature (ambient) 0 to +55 C 3 HOPR Operating Humidity (relative) 10 to 90 % TSTG Storage Temperature -50 to +100 C 1 HSTG Storage Humidity (without condensation) 5 to 95 % 1 PBAR Barometric Pressure (operating LOW: no Autoprecharge). A10 is sampled durin
20、g a Precharge command to determine whether the Precharge applies to one bank (A10 LOW) or all banks (A10 HIGH). If only one bank is to be precharged, the bank is selected by bank addresses. A12 / BC_n Input Burst Chop: A12/BC_n is sampled during Read and Write commands to determine if burst chop (on
21、-the-fly) will be performed. (HIGH, no burst chop; LOW: burst chopped). See command truth table for details. JEDEC Standard No. 248 Page 5 Revision 1.0 RESET_n CMOS Input Active Low Asynchronous Reset: Reset is active when RESET_n is LOW, and inactive when RESET_n is HIGH. RESET_n must be HIGH durin
22、g normal operation. DQ Input/ Output Data Input/ Output: Bi-directional data bus. If CRC is enabled via Mode register then CRC code is added at the end of Data Burst. Any DQ from DQ0-DQ3 may indicate the internal Vref level during test via Mode Register Setting MR4 A4=High. Refer to vendor specific
23、data sheets to determine which DQ is used. DQS0_t-DQS17_t, DQS0_c-DQS17_c Input/ Output Data Strobe: output with read data, input with write data. Edge-aligned with read data, centered in write data. The data strobe DQS_t is paired with differential signals DQS_c, respectively, to provide differenti
24、al pair signaling to the system during reads and writes. DDR4 SDRAM supports differential data strobe only and does not support single-ended. TDQS9_t-TDQS17_t, TDQS9_c-TDQS17_t Input Provides a dummy load for x8 based NVDIMMs where mixed populations of X4 and x8 based NVDIMMs are present. DBI0_n-DBI
25、8_n Input/ Output Provides for data bus inversion. Only possible for x8 based NVDIMMs and where only x8 based NVDIMMs are on a channel. DM0_n-DM8_n Input Provides for masking of a byte on WRITE commands to the SDRAMs. Only possible for x8 based NVDIMMs and where only x8 based NVDIMMs are on a channe
26、l. PAR Input Command and Address Parity Input: DDR4 Supports Even Parity check in SDRAMs with MR setting. Once its enabled via Register in MR5, then SDRAM calculates Parity with ACT_n, RAS_n/A16, CAS_n/A15, WE_n/A14, BG0-BG1, BA0-BA1, A17-A0. Input parity should be maintained at the rising edge of t
27、he clock and at the same time with command & address with CS_n LOW ALERT_n Output (Input) Alert : It has multi functions such as CRC error flag, Command and Address Parity error flag as Output signal. If there is error in CRC, then ALERT_n goes LOW for the period time interval and goes back HIGH. If
28、 there is error in Command Address Parity Check, then ALERT_n goes LOW for relatively long period until ongoing SDRAM internal recovery transaction is complete. During Connectivity Test mode this pin functions as an input. Using this signal or not is dependent on the system. SAVE_n Input (Output) In
29、put: SAVE_n must be high during normal operation. SAVE_n must be high during power on initialization. In default mode, when driven low will initiate a Save operation on the NVDIMM module. Optionally, SAVE_n signal is pulsed 2 times or 3 times in 2 trigger mode and 3 trigger mode, respectively. Outpu
30、t: (Optional) The NVDIMM module may optionally drive SAVE_n low once a save operation been initiated. The NVDIMM module may continue driving SAVE_n low until the save operation is complete. The NVDIMM module will not unilaterally drive the SAVE_n signal low. RFU Reserved for Future Use: No on DIMM e
31、lectrical connection is present. NC No Connect: No on DIMM electrical connection is present. VDD1Supply Power Supply: 1.2V 0.06 V VSS Supply Ground VTT Supply Power Supply for termination of Address, Command and Control, VDD/2. V_12 Supply NVDIMM-N main +12 V supply +/- 15% VPP Supply SDRAM Activati
32、ng Power Supply: 2.5V ( 2.375V min, 2.75V max) VDDSPD Supply Power supply used to power the I2C bus on the SPD-TSE and register. VREFCA Supply Reference voltage for CA 1. For PC4 VDD is 1.2V. For PC4L VDD is TBD. JEDEC Standard No. 248 Page 6 Revision 1.0 3 Connector Pinout and Signal Description (c
33、ontd) Table 5 SAVE_n Signal Characteristics Vih60.7*VDD VDD 0.95 x VDDmin/2 = (0.60 V 0.058 V) = 0.542 2. = 0 ms= 0 ms= 0 ms See SDRAM Standard, (JESD79-4)Clock CKEd RCD (Register) Standard (JESD82-31)JEDEC Standard No. 248 Page 12 Revision 1.0 4.3 Recommended Power Down Sequence Figure 2 Graphical
34、View of Recommended Power Down Sequence Feed Through Voltage (Vft) The normal power down sequence requires the voltage relationships established during power on be maintained. Vft is defined as the voltage delta between VSS and the associated power plane with no power applied to that plane. The abso
35、lute value of this voltage must remain less than 200 mV (|Vft| 0.20 V), which is less than the 300 mV DRAM ramp reference level for start or end of voltage ramp. 4.4 +12 V Power The +12 volt power source is required for NVDIMM-N modules while system power is on to support technologies other than DDR
36、4 SDRAM. Homogeneously populated DRAM modules (i.e., UDIMMs, RDIMMs, and LRDIMMs) may be inserted into sockets that provide 12 V support. The +12 V supply must meet the requirements of 4.1, DIMM Voltage Requirements and 4.2. 12 V Backup power off and Idle power off requirements must be met if module
37、 backup power supplied through V_12. The NVDIMM-N is powered from backup power when the system power is off and a SAVE backup operation has been initiated. Any module which uses 12 V must not interfere with the power sequence(s) of modules that do not support 12 V. 12 V shall remain valid during red
38、uced power modes except it may remain valid during self-refresh. The specific load requirements during these modes are product specific. JEDEC Standard No. 248 Page 13 Revision 1.0 Component Details 5MO-207 allows a maximum SDRAM package height of 21.0 mm. The maximum package size is not required fo
39、r DDR4 NVDIMMs. The larger the SDRAM package the farther it must be placed from the edge connector and the longer the DQ bus must be. Minimizing the SDRAM package size to what is actually required improves signal integrity. Decoupling is improved if the capacitors are placed closer to the SDRAM ball
40、s. Power delivery is improved with a reduction in width of the SDRAMs to what is actually required. See 6.7.3, SDRAM Package Size for target SDRAM package size. Figure 3 DIMM Ball Patterns for DDR4 SDRAM Components shows the mechanical information for the DDR4 SDRAM components. To use a smaller SDRA
41、M component some or all of the mechanical support balls may be omitted. Figure 3 DIMM Ball Patterns for DDR4 SDRAM Components x8 Maximum Dimensions and Support Ball LocationsJEDEC Standard No. 248 Page 14 Revision 1.0 5 Component Details (contd) Table 8 DDR4 x4 SDRAM DIMM Pad Array Top view MO-207 v
42、ariation DW-z 1 2 3 4 8 9 10 11 A NC1NC1NC1NC1NC1NC1B C NC1NC1NC1NC1NC1NC1D E F NC1VDD VSSQ NC2NC3VSSQ VSS NC1A G VPP VDDQ DQS_c DQ1 VDDQ ZQ B H VDDQ DQ0 DQS_t VDD VSS VDDQ C J VSSQ NC4DQ2 DQ3 NC4VSSQ D K VSS VDDQ NC4NC4VDDQ VSS E L VDD C2, ODT1 ODT CK_t CK_c VDD F M VSS C0, CKE1 CKE CS_n C1, CS1_n
43、TEN7G N VDD A14/WE_n ACT_n A15/CAS_n A16/RAS_n VSS H P VREFCA BG0 A10/AP A12/BC_n BG1 VDD J R VSS BA0 A4 A3 BA1 VSS K T RESET_n A6 A0 A1 A5 ALERT_n L U VDD A8 A2 A9 A7 VPP M V NC1VSS A11 PAR5A176A13 VDD NC1N W 1 2 3 7 8 9 Y MO-207 variation DT-z AA NC1NC1NC1NC1NC1NC1AB AC NC1NC1NC1NC1NC1NC11. These
44、balls are mechanical support balls for large SDRAM packages. A pad array to support MO-207 variation DT-z will not include these balls. 2. TDQS_c is not valid on x4 based SDRAM components. 3. DM_n, DBI_n and TDQS_t are not valid on x4 based SDRAM components. 4. DQ4, DQ5, DQ6 and DQ7 are not valid fo
45、r x4 based SDRAM components. 5. Parity input for address parity. 6. A17 is only valid for x4 based SDRAMs of 16G bits. 7. TEN is a test enable pin. It is not used on NVDIMMs and should be tied low. JEDEC Standard No. 248 Page 15 Revision 1.0 5 Component Details (contd) Table 9 DDR4 x8 SDRAM DIMM Pad
46、 Array Top view MO-207 variation DW-z 1 2 3 4 8 9 10 11 A NC1NC1NC1NC1NC1NC1B C NC1NC1NC1NC1NC1NC1D E F NC1VDD VSSQ TDQS_c, NC2TDQS_t, DBI_n, DM_n, NC3VSSQ VSS NC1A G VPP VDDQ DQS_c DQ1 VDDQ ZQ B H VDDQ DQ0 DQS_t VDD VSS VDDQ C J VSSQ DQ4 DQ2 DQ3 DQ5 VSSQ D K VSS VDDQ DQ6 DQ7 VDDQ VSS E L VDD C2, OD
47、T1 ODT CK_t CK_c VDD F M VSS C0, CKE1 CKE CS_n C1, CS1_n TEN6G N VDD A14/WE_n ACT_n A15/CAS_n A16/RAS_n VSS H P VREFCA BG0 A10/AP A12/BC_n BG1 VDD J R VSS BA0 A4 A3 BA1 VSS K T RESET_n A6 A0 A1 A5 ALERT_n L U VDD A8 A2 A9 A7 VPP M V NC1VSS A11 PAR4A175A13 VDD NC1N W 1 2 3 7 8 9 Y MO-207 variation DT
48、-z AA NC1NC1NC1NC1NC1NC1AB AC NC1NC1NC1NC1NC1NC11. These balls are mechanical support balls for large SDRAM packages. A pad array to support MO-207 variation DT-z will not include these balls. 2. NC is valid for x8 based NVDIMMs only when TDQS is disabled. 3. NC is valid functions for x8 based NVDIM
49、Ms only when DM, DBI and TDQS are disabled. 4. Parity input for address parity. 5. A17 is only valid for x4 based SDRAMs of 16G bits. 6. TEN is a test enable pin. It is not used on NVDIMMs and should be tied low. JEDEC Standard No. 248 Page 16 Revision 1.0 5.1 Component Types and Placement Components shall be positioned on the PCB to meet the minimum and maximum trace lengths required for DDR4 SDRAM signals. Bypass capacitors for DDR4 SDRAM devices must be located near the device power pins. 5.2 Decoupling
