1、Jednoduch obvody ve VHDL,Pevzato z materil kurzu INP 2003,INP,2,Pklad: Multiplexor (mpx8) popis chovn,mpx8,y,s(1),s(0),s(2),din,0,7,P.: Kdy s=1 potom y=din(1),INP,3,library IEEE; use IEEE.std_logic_1164.all;entity mpx8 isport (din: in STD_LOGIC_VECTOR (7 downto 0); s: in STD_LOGIC_VECTOR (2 downto 0
2、); y: out STD_LOGIC); end mpx8;architecture mpx8 of mpx8 is begin process (s, din) variable ss: STD_LOGIC_VECTOR (2 downto 0); - pomocn promnn begin ss(0) := s(0); ss(1) := s(1); ss(2) := s(2);case ss is when “000“ = y y y y y y y y y = X; end case; end process; end mpx8;,rozhran,chovn,knihovny,INP,
3、4,Test bench pro mpx8 (automatick test komponenty),mpx8,y,s1,s0,s2,din,0,7,Genertor testu,INP,5,entity tb_mpx8 is - nem rozhran end tb_mpx8;architecture arch_tb_mpx8 of tb_mpx8 is signal din: STD_LOGIC_VECTOR (7 downto 0); - potebn signly signal s: STD_LOGIC_VECTOR (2 downto 0); signal y: STD_LOGIC;
4、 component mpx8 - testovan jednotkaport (din: in STD_LOGIC_VECTOR (7 downto 0); s: in STD_LOGIC_VECTOR (2 downto 0); y: out STD_LOGIC );end component;begin UUT : mpx8 port map (din = din, s = s, y = y); - pipojen process begin - vlastn test din = “01010101“; s = “000“; wait for 10 ns; s = “001“; wai
5、t for 10 ns; s = “010“; wait for 10 ns; s = “011“; wait for 10 ns; s = “100“; wait for 10 ns; s = “101“; wait for 10 ns; s = “110“; wait for 10 ns; s = “111“; wait for 10 ns; end process; end arch_tb_mpx8;,INP,6,Mpx8 strukturln (mpx8s.vhd),&,&,&,&,&,&,&,&,1,y,Potebujeme: 8 x 4vst. AND 1 x 8vst. OR 3
6、 x invertor ns(j) = not s(j),a0out,a3out,a4out,a5out,a6out,a7out,a1out,a2out,INP,7,And4.vhd,library IEEE; use IEEE.std_logic_1164.all;entity and4 isport (a1: in std_logic;a2: in std_logic;a3: in std_logic;a4: in std_logic;b: out STD_LOGIC ); end and4;architecture and4 of and4 is beginb = a1 and a2 a
7、nd a3 and a4; end and4;,INP,8,mpx8s.vhd,Vyzkouejte si mpx8s.vhd v ModelSimu msto mpx8.vhd. Jako test bench pouijte tb_mpx.vhd.,INP,9,Struktura VHDL kdu,library IEEE; entity name isport (); end name;architecture struc of name is signal ns0 : std_logic;component and4 port (); end component;begin ns2 =
8、 not s(2);aa0: and4 port map ();P0: process (a,b) begin end process;P1: process begin end process; end struc;,knihovny,definice rozhran,popis innosti komponenty,Deklarace signl pro propojovn komponent a komunikaci proces.,Deklarace komponent.,Zde jsou jen paraleln pkazy“!,mapovn komponenty na signly
9、,Uvnit procesu lze ut sekvenn pkazy a pouvat promnn.,INP,10,library IEEE; use IEEE.std_logic_1164.all;entity dec3to8 isport (addr: in STD_LOGIC_VECTOR (2 downto 0);y: out STD_LOGIC_VECTOR (7 downto 0); end dec3to8;architecture dec3to8 of dec3to8 is beginwith addr selecty = “10000000“ when “111“,“010
10、00000“ when “110“,“00100000“ when “101“,“00010000“ when “100“,“00001000“ when “011“,“00000100“ when “010“,“00000010“ when “001“,“00000001“ when others; end dec3to8;,Dekodr,INP,11,- HEX: in STD_LOGIC_VECTOR (3 downto 0); - LED: out STD_LOGIC_VECTOR (6 downto 0); - 0 - - - 5 | | 1 - - - 6 - 4 | | 2 -
11、- - 3with HEX selectLED= “1111001“ when “0001“, -1“0100100“ when “0010“, -2“0110000“ when “0011“, -3“0011001“ when “0100“, -4“0010010“ when “0101“, -5“0000010“ when “0110“, -6“1111000“ when “0111“, -7“0000000“ when “1000“, -8“0010000“ when “1001“, -9“0001000“ when “1010“, -A“0000011“ when “1011“, -b
12、“1000110“ when “1100“, -C“0100001“ when “1101“, -d“0000110“ when “1110“, -E“0001110“ when “1111“, -F“1000000“ when others; -0,Dekodr pro 7-segmentovku,INP,12,Klopn obvod typu D,library IEEE; use IEEE.std_logic_1164.all;entity dffx isport ( CLK : in std_logic;RSTn : in std_logic;DATA : in std_logic;Q
13、OUT : out std_logic ); end dffx;architecture behavr1 of dffx is begin process (CLK,RSTn) beginif (RSTn=0) then - asynchronni resetQOUT = 0;elsif (CLKevent and CLK = 1) thenQOUT = DATA; end if; end process; end behavr1;,Asynchronn reset, aktivn pi 0,D,CLK,QOUT,Q,RSTn,DATA,INP,13,Asynchronn reset u KO
14、 typu D,process (CLK, RESET) beginif RESET=1 then -asynchronous RESET active HighDOUT = 0;elsif (CLKevent and CLK=1) then -CLK rising edgeDOUT = DIN;end if; end process;,CLK,RESET,DOUT,DIN=1,D,CLK,Q,Q,RESET,DIN,DOUT,INP,14,Synchronn reset u KO typu D,process (CLK) begin if CLKevent and CLK=1 then -C
15、LK rising edgeif RESET=1 then -synchronous RESET active HighDOUT = 0;elseDOUT = DIN;end if; end if; end process;,CLK,RESET,DOUT,DIN=1,INP,15,Klopn obvod JK,entity JKFF isport (CLK, RSTn, J, K : in bit;Q : out bit); end JKFF; - architecture RTL of JKFF issignal FF : bit; beginprocess (CLK, RSTn)varia
16、ble JK : bit_vector(1 downto 0);beginif (RSTn = 0) thenFF FF FF FF FF = FF;end case;end if; end process;Q = FF; end RTL;,INP,16,Registr s asynchronnm nulovnm,- 4-bit parallel load register with asynchronous reset - CLK: in STD_LOGIC; - ASYNC: in STD_LOGIC; - LOAD: in STD_LOGIC; - DIN: in STD_LOGIC_V
17、ECTOR(3 downto 0); - DOUT: out STD_LOGIC_VECTOR(3 downto 0);process (CLK, ASYNC) beginif ASYNC=1 thenDOUT = “0000“;elsif CLK=1 and CLKevent thenif LOAD=1 thenDOUT = DIN;end if;end if; end process;,INP,17,Posuvn registr,- 4-bit serial-in and serial-out shift register - CLK: in STD_LOGIC; - DIN: in ST
18、D_LOGIC; - DOUT: out STD_LOGIC;process (CLK)variable REG: STD_LOGIC_VECTOR(3 downto 0); beginif CLKevent and CLK=1 then REG := DIN ,INP,18,clk,1,Posuvn registr a vnon stromeek,INP,19,Cvien,Popite a simulujte pomoc VHDL obvod pro zen vnonho stromeku.,INP,20,Cyklick ta 0-7 (toto rozhran je stejn pro s
19、trukturn i behaviorln popis),library IEEE; use IEEE.std_logic_1164.all;entity cnt07 isport (CLK: in STD_LOGIC;RESET: in STD_LOGIC;COUNT: out STD_LOGIC_VECTOR (2 downto 0); end cnt07;,CNT0-7,CLK,RESET,COUNT,INP,21,Cyklick ta 0-7 (strukturn popis, st 1),architecture struct of cnt07 is component dffx p
20、ort ( CLK : in std_logic;RSTn : in std_logic;DATA : in std_logic;QOUT : out std_logic ); end component;signal Q0 : std_logic; - vystup Q KO D signal Q1: std_logic; - vystup Q KO D signal Q2: std_logic; - vystup Q KO D signal D0 : std_logic; - vstup D KO D signal D1: std_logic; - vstup D KO D signal
21、D2: std_logic; - vstup D KO D,Strukturn popis nen v tomto ppad vhodn pout, protoe musme udlat nejdve nvrh na pape a podle toho vytvoit VHDL popis.Budeme potebovat 3x KO D a uveden vodie,INP,22,Cyklick ta 0-7 (strukturn popis, st 2),begin ff0 : dffx - KO D nejni bit tae port map ( CLK = CLK, RSTn = R
22、ESET, DATA = D0, QOUT = Q0 );ff1 : dffx - KO D prostedn bit tae port map ( CLK = CLK, RSTn = RESET, DATA = D1, QOUT = Q1 );ff2 : dffx - KO D nejvy bit tae port map ( CLK = CLK, RSTn = RESET, DATA = D2, QOUT = Q2 );- vytvoen vstup KO podle schmatu D0 = not Q0; D1 = Q0 xor Q1; D2 = (not Q0 and Q2) or
23、(not Q1 and Q2) or (Q0 and Q1 and not Q2); COUNT = Q2 ,INP,23,Vsledek simulace,INP,24,ta 0-7 (behaviorln popis),architecture beh of cnt07 is beginprocess (CLK, RESET) variable COUNT_INT: STD_LOGIC_VECTOR(2 downto 0); begin if RESET = 0 then COUNT_INT := “000“; elsif CLK=1 and CLKevent then if COUNT_
24、INT = “111“ then COUNT_INT := “000“; elseCOUNT_INT := COUNT_INT + 1; end if; end if; COUNT = COUNT_INT; end process; end beh;,Tmto zpsobem se obvykle popisuj tae ve VHDL.,INP,25,- LOAD: in STD_LOGIC; DIR: in STD_LOGIC; - DIN: in STD_LOGIC_VECTOR (3 downto 0); - COUNT: out STD_LOGIC_VECTOR (3 downto
25、0) process (CLK, RESET) variable COUNT_INT: STD_LOGIC_VECTOR(3 downto 0); begin if RESET = 1 then COUNT_INT := (others = 0); elsif CLK=1 and CLKevent then if LOAD = 1 then COUNT_INT := DIN;elseif CE = 1 then if DIR = 1 then -count upif COUNT_INT = “1111” then COUNT_INT := (others = 0); elseCOUNT_INT
26、 := COUNT_INT + 1; end if; else -count downif COUNT_INT = “0000” then COUNT_INT := (others = 1); elseCOUNT_INT := COUNT_INT - 1; end if; end if;end if; end if;end if; COUNT = COUNT_INT; end process;,Obousmrn (DIR) synchronn ta s pedvolbou po. stavu (LOAD) a s povolenm innosti (CE),INP,26,Cvien,Popit
27、e a simulujte pomoc VHDL obvod, kter bude generovat cyklicky sla 0 F na sedmisegmentovce. Npovda: pouijte ta a dekodr.,INP,27,Pklad: adi pamti,Navrhnte a ve VHDL simulujte adi pamti, kter pracuje podle zadanho automatu. Napite test bench, kterm ovte jeho funkci.,INP,28,adi pamti,CPU,adi,pam,ready,Rd
28、Wr,rst,clk,rd,wr,Klid/11,ten/01,zpis/10,Volba/11,0X,0X,1X,1X,1X,0X,X1,X0,stav/rd,wr,Ready,RdWr,Vznam:,rst,INP,29,adi pamti,entity RdWrMoo is port(ready, RdWr, Rst, Clk : in std_logic;Rdnt, Wrnt : out std_logic ); end RdWrMoo; architecture beh of RdWrMoo istype StateType is (Klid, Volba, Zapis, Cteni
29、); signal PresentState, NextState : StateType; - soucasny a pristi stav signal Rw: std_logic_vector(1 downto 0); - pomocny signal (vystupy)begin Rdnt = Rw(1); Wrnt = Rw(0);- stavovy regist Clock: process (Clk) beginif (clkevent and clk = 1) thenPresentState = NextState;end if; end process Clock;,INP
30、,30,Comb: process (PresentState, Ready, RdWr, Rst) begin case PresentState iswhen Klid = Rw Rw Rw Rw =“01“;if Ready = 1 then NextState = Klid;else NextState = Cteni;end if; end case; if Rst = 1 then NextState = Klid; end if; end process Comb; end beh;,Klid/11,Volba/11,1X,0X,rst,zpis/10,0X,X0,ten/01,
31、0X,1X,X1,1X,INP,31,Test bench,entity tb_radic is end tb_radic;architecture beh of tb_radic is signal ready, RdWr, Rst, Clk : std_logic; signal Rdnt, Wrnt : std_logic;component RdWrMoo port ( ready,RdWr,Rst,Clk : in std_logic;Rdnt,Wrnt : out std_logic );end component;begin UUT : RdWrMoo - “instance“
32、testovane jednotky port map (ready = ready, RdWr = RdWr, Rst = Rst,Clk = Clk,Rdnt = rdnt,Wrnt = Wrnt);process begin Rst = 1; Ready = 0; RdWr = 0; clk = 0;wait for 5 ns; Rst = 0;clk = 1; wait for 10 ns; clk = 0; wait for 7 ns;Ready = 1; wait for 3 ns; clk = 1; wait for 10 ns; clk = 0; wait for 10 ns;
33、 Ready = 0;clk = 1; wait for 10 ns; clk = 0; wait for 10 ns; Ready = 1;clk = 1; wait for 10 ns; clk = 0; wait for 10 ns; clk = 1; wait for 10 ns; clk = 0; wait for 10 ns; clk = 1; wait for 10 ns; clk = 0; wait for 10 ns; clk = 1; wait for 10 ns; clk = 0; wait for 10 ns; RdWr = 1;clk = 1; wait for 10
34、 ns; clk = 0; wait for 10 ns; clk = 1; wait for 10 ns; clk = 0; wait for 10 ns; end process; end beh;,INP,32,asov prbh pro zvolen vstupy,Test bench je k dispozici na webovsk strnce cvien.,INP,33,Vytvoen obvod,kombinan logika,KO,KO,kombinan logika vstupu,rd,wr,ready,RdWr,clk,rst,stav/rd,wr,Ready,RdWr
35、,stavov registr,INP,34,K zadn projektu . 1,Zadn: viz www kurzu, upozornn P. Prce s polem (pamt, registry) 16 x 32b,- knihovny pro konverze library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all;signal data32, out32: std_logic_vector (31 downto 0); si
36、gnal addr: std_logic_vector (3 downto 0);- nov typ: pole registr type RegArrayType is array (15 downto 0) of std_logic_vector(31 downto 0); - instance promnn tohoto typu signal RegArray: RegArrayType;- prce s polem RegArray(conv_integer(addr) = data32; - zpis Out32 = RegArray(conv_integer(addr); - t
37、en,INP,35,Literatura,Kolouch, J.: Programovateln logick obvody a modelovn slicovch systm v jazycch ABEL a VHDL. Skriptum VUT v Brn, 2000. Plva, Z., Kol, M.: Pednky pedmtu Elektronick zazen. TU Liberec, 2002 Chang, K. C.: Digital Design and Modeling with VHDL and Synthesis. IEEE Computer Society, Los Alamitos 1997 Chang, K. C.: Digital Systems Design with VHDL and Synthesis: An Integrated Approach. IEEE Computer Society, Los Alamitos and John Wiley 1999 Internet: viz odkazy na domovsk strnce kurzu,
