1、A Roadmap and Vision for Physical Design ISPD-2002 April 9, 2002 Andrew B. Kahng, UCSD CSE & ECE Departments email: abkucsd.edu URL: http:/vlsicad.ucsd.edu,Outline,What we need ITRS challenges, logical/circuit/physical needs SRC needs What we do Allocation of effort, versus needs and resources Harmf
2、ul practices What we need to do Coopetition Shared red bricks What we need to do, II A top-10 list,The “Red Brick Wall” - 2001 vs. 1999,Source: Semiconductor International - http:/www.e- Acceleration and Deceleration,Year of Production: 1999 2002 2005 2008 2011 2014 DRAM Half-Pitch nm: 180 130 100 7
3、0 50 35 Overlay Accuracy nm: 65 45 35 25 20 15 MPU Gate Length nm: 140 85-90 65 45 30-32 20-22 CD Control nm: 14 9 6 4 3 2 TOX (equivalent) nm: 1.9-2.5 1.5-1.9 1.0-1.5 0.8-1.2 0.6-0.8 0.5-0.6 Junction Depth nm: 42-70 25-43 20-33 16-26 11-19 8-13 Metal Cladding nm: 17 13 10 000 Inter-Metal Dielectric
4、 K: 3.5-4.0 2.7-3.5 1.6-2.2 1.5,2001 versus 1999,Source: A. Allan, Intel,An ITRS Analogy,ITRS is like a car Before, two drivers (husband = MPU, wife = DRAM) The drivers looked mostly in the rear-view mirror (destination = “Moores Law”) Many passengers in the car (ASIC, SOC, Analog, Mobile, Low-Power
5、, Networking/Wireless, ) wanted to go different places This year: Some passengers became drivers All drivers explain more clearly where they are going See the new “System Drivers” Chapter of the ITRS,HP / LOP / LSTP Device Roadmaps,Silicon Complexity Challenges,Impact of process scaling, new materia
6、ls, new device/interconnect architectures Non-ideal scaling (leakage, power management, circuit/device innovation, current delivery) Coupled high-frequency devices and interconnects (signal integrity analysis and management) Manufacturing variability (library characterization, analog and digital cir
7、cuit performance, error-tolerant design, layout reusability, static performance verification methodology/tools) Scaling of global interconnect performance (communication, synchronization) Decreased reliability (SEU, gate insulator tunneling and breakdown, joule heating and electromigration) Complexi
8、ty of manufacturing handoff (reticle enhancement and mask writing/inspection flow, manufacturing NRE cost),System Complexity Challenges,Exponentially increasing transistor counts, with increased diversity (mixed-signal SOC, ) Reuse (hierarchical design support, heterogeneous SOC integration, reuse o
9、f verification/test/IP) Verification and test (specification capture, design for verifiability, verification reuse, system-level and software verification, AMS self-test, noise-delay fault tests, test reuse) Cost-driven design optimization (manufacturing cost modeling and analysis, quality metrics,
10、die-package co-optimization, ) Embedded software design (platform-based system design methodologies, software verification/analysis, codesign w/HW) Reliable implementation platforms (predictable chip implementation onto multiple fabrics, higher-level handoff) Design process management (team size / g
11、eog distribution, data mgmt, collaborative design, process improvement),Big-Picture Design Technology Crises,Manufacturing,NRE Cost,SW Design,Verification,HW Design,Test,Turnaround Time,Manufacturing,Incremental Cost Per Transistor,2-3X more verification engineers than designers on microprocessor te
12、ams Software = 80% of system development cost (and Analog design hasnt scaled) Design NRE 10s of $M manufacturing NRE $1M Design TAT = months or years manufacturing TAT = weeks Without DFT, test cost per transistor grows exponentially relative to mfg cost,Where is the Physical Design?,SRC Grand Chal
13、lenges,1. Extend CMOS to its ultimate limit 2. Support continuation of Moores Law by providing a knowledge base for CMOS replacement devices 3. Enable Wireless/Telecomm systems by addressing technical barriers in design, test, process, device and packaging technologies 4. Create mixed-domain transis
14、tor and device interconnection technologies, architectures, and tools for future microsystems that mitigate the limitations projected by ITRS 5. Search for radical, cost effective post NGL patterning options 6. Provide low-cost environmentally benign IC processes 7. Increase factory capital utilizat
15、ion efficiency through operational modeling 8. Provide design tools and techniques which enhance design productivity and reduce cost for correct, manufacturable and testable SOCs and SOPs 9. Enable low power and low voltage solutions for mobile/battery conserving applications through system and circ
16、uit design, test and packaging approaches. 10. Enable very low cost components 11. Provide tools enabling rapid implementation of new system architectures,Where is the Physical Design?,SRC ICSS Key Technologies (Top 12),Systems S3.2: Early Design Space Exploration S1.2: Low Power, Real-Time Algorith
17、ms and Architectures S4.1: On-Chip Communication S1.3: High Bandwidth and/or Low Power Communication S2.4: Deep Submicron Aware Microarchitectures, Accounting for Noise, Power, Timing, Interconnects, etc. S1.1: High Level Specifications of Complex Systems,Circuits C1.2: Digital Low Power and/or Low
18、Voltage Circuit Design C2.1: Mixed Signal Circuits on Advanced Technologies C2.4: Mixed Signal Low Power and/or Low Voltage Circuit Design C1.1: Digital Circuits on Advanced Technologies C2.3: Mixed Signal Design for Test C2.2: Mixed Signal Noise Immune and/or Tolerant Circuits,Where is the Physical
19、 Design?,ITRS Logical/Physical/Circuit Challenges,Efficient and predictable implementation Scalable, incremental analyses and optimizations Unified implementation/interconnect planning and estimation/prediction Synchronization and global signaling Heterogeneous system composition Links to verificati
20、on and test Reliable, predictable fabric- and application-specific silicon implementation platforms Cost-driven implementation flows Variability and design-manufacturing interface Uncertainty of fundamental chip parameters (timing, skew, matching) due to manufacturing and dynamic variability sources
21、 Process modeling and characterization Cost-effective circuit, layout and reticle enhancement to manage manufacturing variability Increasing atomic-scale variability effects,Silicon complexity, non-ideal device scaling and power management Leakage and power management Reliability and fault tolerance
22、 Analysis complexity and consistent analyses / synthesis objectives Recapture of reliability lost in manufacturing test Circuit design to fully exploit device technology innovation Support for new circuit families that address power and performance challenges Implementation tools for SOI Analog synt
23、hesis Increasing atomic-scale effects Adaptive and self-repairing circuits Low-power sensing and sensor interface circuits; micro-optical devices,ITRS Logical/Physical/Circuit Challenges,SRC CADT PD Research Needs (2002 Draft),Placement and Routing Synthesis/Layout Integration Power Distribution and
24、 Analysis High Level Planning and Estimation Clocking Design and Analysis Above 15GHz Interconnect Synthesis and Analysis Timing Analysis and Verification Correct by Construction,Where are the ITRS challenges?,Outline,What we need ITRS challenges, logical/circuit/physical needs SRC needs What we do
25、Allocation of effort, versus needs and resources Harmful practices What we need to do Coopetition Shared red bricks What we need to do, II A top-10 list,Our Resources,6000 EDA R&D, worldwide (Gartner/Dataquest) EDA tools revenue per designer has increased by 3.9% per year over past decade Ratio of d
26、esign value over design effort is perceived to decrease as level of abstraction moves downward from behavior to layout PD is at most one-sixth (by market size, or by headcount) of EDA and design technology 150-200 ISPD attendees, 60 DAC/ICCAD/ISPD papers in PD domain, per year,Research Funding Gap S
27、tudy,C. Nuese, SRC Research needs Time frame 2008+ (50-, 35-, and 22-nm nodes in ITRS) Assessed by SRC Science Area Directors (131 total tasks) Research funding 2001 used for all data U.S., Europe, Japan and Asia-Pacific Assumed % of R&D (or % of Sales),Source: C. Nuese / SRC,Funding Model,Source: C
28、. Nuese / SRC,Research Funding Gap Results,Foreign redundancy and inaccessibility significantly increase size of effective research gap.,Source: C. Nuese / SRC,Anatomy of ITRS PD Needs,Analog layout synthesis and reuse Layout-BIST synergies for UDSM fault models New paradigms for global signaling, s
29、ynchronization and system-level interconnect Modeling and simulation Mitigation of increased process variability and non-recurring costs in mask and foundry flows Multi-(Vdd, Vt, tox, biasing) performance optimization ,Anatomy of Recent PD Literature,(1) placement / partitioning (2) routing / global
30、 routing / wireplanning (3) interconnect tree (buffered / Steiner / RAT / ) construction (4) floorplanning / block packing / macro-cell placement (5) performance optimization (sizing, etc.) (6) RTL-down methodology / flow (7) clock (8) power (9) custom layout (transistor-level / migration / compacti
31、on) (10) analog (11) manufacturability / yield (12) logical-physical interactions (13) signal integrity Table: DAC (Y) / ICCAD (Y) / ISPD (Y+1), in Y = 1996, , 2001,Distribution of Physical Design Papers Among 13 Topics,Where are the ITRS challenges?,Dissimilarity by Compression ,(ISPD97 + CADT).gz
32、CADT.gz) / ISPD97.gz(ISPD97 + ISPD02).gz ISPD02.gz) / ISPD97.gz = 0.78,Outline,What we need ITRS challenges, logical/circuit/physical needs SRC needs What we do Allocation of effort, versus needs and resources Harmful practices What we need to do Coopetition Shared red bricks What we need to do, II
33、A top-10 list,What Is Going On Here?,Three pernicious phenomena (1) Long lead times and latencies: formulation to solution to technology transfer to marketplace (2) High startup costs and other barriers to entry in research (3) Research field recreates itself in its own image,Its Not A Moving Target
34、,PD roadmap has been static Convergent integration of logic, timing, spatial embedding Unification of incremental timing/SI closure with PA backplane Methodology and routing contexts Some references NTRS/ITRS since 1994 1995 Sematech CHDS specification L. Scheffer, PDW96: “Were Solving the Wrong Pro
35、blems” Other examples listed in paper,Hello?,Hello?,Too Much Back-Filling?,Practice of putting well-known and already commercialized techniques into the public literature Some impact on IP and research efficiency, but only if there is adequate transfer of the resulting technology! Standard planning
36、framework, next-generation detailed routers, etc. are better left to industry Academia would benefit from more industry-strength shared research infrastructures,What Should Be Novel in Research?,Novelty in formulation, or novelty in optimization? Claim: PD is focusing more on “novel” problem stateme
37、nts, while only transferring or reusing core optimization techniques 15+ years ago: PD was the source of simulated annealing, LP relaxation/rounding, hierarchical routing, etc. Past decade: mostly transferring methods (e.g., multilevel (PDW96, DAC97) Again: “Were solving the wrong problems” Cf. “pac
38、king obsession” in floorplanning literature Shortage of optimization tools No shortage of problems,Outline,What we need ITRS challenges, logical/circuit/physical needs SRC needs What we do Allocation of effort, versus needs and resources Harmful practices What we need to do Mindset Change #1: Coopet
39、ition Mindset Change #2: Shared red bricks What we need to do, II A top-10 list,Vision: Improved Design Technology Productivity,MARCO GSRC Calibrating Achievable Design theme http:/vlsicad.ucsd.edu/GSRC/ Improved design technology planning (“specify”): What will the design problem look like? What do
40、 we need to solve? Improved execution (“develop”): How can we quickly (TTM) develop the right design technology (QOR)? Reusable, commodity, foundation CAD-IP (+ new publication standards) Improved measurement (“measure and improve” ): Did we solve the problem (QOR)? Did the design process improve? D
41、id we increase the envelope of achievable design? Design tool/process metrics, design process instrumentation and continuous process improvement Ethos of “coopetition” (cooperation among competitors),“Living ITRS” Framework,CAD-IP Reuse,Rapid development and evaluation of fundamental algorithm techn
42、ology, via CAD-IP reuse CAD-IP = Data models and benchmarks context descriptions and use models testcases and good solutions CAD-IP = Algorithms and algorithm analyses mathematical formulations comparison and evaluation methodologies for algorithms executables and source code of implementations lead
43、ing-edge performance results CAD-IP = Traditional (paper-based) publications,MARCO GSRC Bookshelf: A Repository for CAD-IP,New element of VLSI CAD culture “Community memory” currently centered in back-end data models, algorithms, implementations repository for open-source “foundation CAD-IP” Publica
44、tion medium that supports efficient CAD R&D benchmarks, performance results algorithm descriptions and analyses quality implementations (e.g., open-source UCLA PDTools) Enables comparisons to identify best approaches Enables communication by industry of use models, problem formulations http:/gigasca
45、le.org/bookshelf/ Have you open-sourced your code in the Bookshelf?,Outline,What we need ITRS challenges, logical/circuit/physical needs SRC needs What we do Allocation of effort, versus needs and resources Harmful practices What we need to do Mindset Change #1: Coopetition Mindset Change #2: Shared
46、 red bricks What we need to do, II A top-10 list,What Is A “Red Brick” ?,Red Brick = ITRS Technology Requirement with no known solutionAlternate definition: Red Brick = something that REQUIRES billions of dollars in R&D investment,Another ITRS Analogy,ITRS technologies are like parts of the carEvery
47、 one takes the “engine” point of view when it defines its requirements “Why, you may take the most gallant sailor, the most intrepid airman, the most audacious soldier, put them at a table together what do you get? The sum of their fears.” - Winston ChurchillAll parts must work together to make the
48、car go smoothlyNeed global optimization of resource allocations with respect to requirements shared red bricks,“Design-Manufacturing Integration”,2001 ITRS Design Chapter: “Manufacturing Integration” = one of five Cross-Cutting Challenges Goal: share red bricks with other ITRS technologies Lithograp
49、hy CD variability requirement new Design techniques that can better handle variability Mask data volume requirement solved by Design-Mfg interfaces and flows that pass functional requirements, verification knowledge to mask writing and inspection ATE cost and speed red bricks solved by DFT, BIST/BOST techniques for high-speed I/O, signal integrity, analog/MS Does “X initiative” have as much impact as copper?,
