1、 REVISIONS LTR DESCRIPTION DATE APPROVED A Update boilerplate paragraphs to current requirements. - PHN 10-01-19 Thomas M. Hess Prepared in accordance with ASME Y14.24 Vendor item drawing REV A A A A PAGE 40 41 42 43 REV A A A A A A A A A A A A A A A A A A A A A A PAGE 18 19 20 21 22 23 24 25 26 27
2、28 29 30 31 32 33 34 35 36 37 38 39 REV STATUS OF PAGES REV A A A A A A A A A A A A A A A A A PAGE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 PMIC N/A PREPARED BY Phu H. Nguyen DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO 43218-3990 Original date of drawing CHECKED BY Phu H. Nguyen TITLE MICROCIRCU
3、IT, DIGITAL, FIXED POINT DIGITAL SIGNAL PROCESSOR, MONOLITHIC SILICON YY MM DD 04-02-11 APPROVED BY Thomas M. Hess SIZE A CODE IDENT. NO. 16236 DWG NO. V62/04607 REV A PAGE 1 OF 43 AMSC N/A 5962-V022-10 .Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-
4、,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04607 REV A PAGE 2 1. SCOPE 1.1 Scope. This drawing documents the general requirements of a high performance Fixed-Point Digital Signal Processor microcircuit, with an operating temperature range of -40C to +85C
5、. 1.2 Vendor Item Drawing Administrative Control Number. The manufacturers PIN is the item of identification. The vendor item drawing establishes an administrative control number for identifying the item on the engineering documentation: V62/04607 - 01 X E Drawing Device type Case outline Lead finis
6、h number (See 1.2.1) (See 1.2.2) (See 1.2.3) 1.2.1 Device type(s). 1/ Device type Generic Circuit function 01 SM320VC5421-EP Fixed Point Digital Signal Processor 1.2.2 Case outline(s). The case outlines are as specified herein. Outline letter Number of pins Package style X 144 Low Profile Quad Flatp
7、ack 1.2.3 Lead finishes. The lead finishes are as specified below or other lead finishes as provided by the device manufacturer: Finish designator Material A Hot solder dip B Tin-lead plate C Gold plate D Palladium E Gold flash palladium Z Other 1.3 Absolute maximum ratings. 2/ Supply voltage I/O ra
8、nge, (DVDD) . -0.5 V to +4.0 V Supply voltage core range, (CVDD) . -0.5 V to +2.4 V Supply voltage analog PLL range, (AVDD) -0.5 V to +2.4 V Input voltage range, (VI) . -0.5 V to DVDD+0.5 V Output voltage range (VO) . -0.5 V to DVDD+0.5 V Operating case temperature ranges, (TC) -40C to +85C Storage
9、temperature range, (TSTG) -65C to +150C 1/ Users are cautioned to review the manufacturers data manual for additional user information relating to this device. 2/ Stresses beyond those listed under “absolute maximum rating” may cause permanent damage to the device. These are stress ratings only, and
10、 functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values are with respect to VSS.Provided b
11、y IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04607 REV A PAGE 3 1.4 Recommended operating conditions. 3/ 4/ Device supply voltage, I/O (DVDD) +3.0 V to +3.6 V Device supp
12、ly voltage, core (CVDD) +1.75 V to +1.98 V Device supply voltage, PLL (AVDD) +1.75 V to +1.98 V Supply voltage, GND (VSS) . 0 V High level input voltage, I/O (VIH): Schmitt triggered inputs, DVDD= 3.3 0.3 V 0.7DVDDto DVDDAll other inputs 2.0 V to DVDDLow level input voltage, I/O (VIL): Schmitt trigg
13、ered inputs, DVDD= 3.3 0.3 V 0 V to 0.3DVDDAll other inputs 0 V to + 0.8 V High level output current, (IOH) . -300 A maximum Low level output current, (IOL) . 1.5 mA maximum Operating case temperature (TC) . -40C to +85C Junction to case (RJC) . 5C/W Junction to air (RJA) 56C/W 2. APPLICABLE DOCUMEN
14、TS JEDEC PUB 95 Registered and Standard Outlines for Semiconductor Devices (Applications for copies should be addressed to the Electronic Industries Alliance, 2500 Wilson Boulevard, Arlington, VA 22201-3834 or online at http:/www.jedec.org) 3. REQUIREMENTS 3.1 Marking. Parts shall be permanently and
15、 legibly marked with the manufacturers part number as shown in 6.3 herein and as follows: A. Manufacturers name, CAGE code, or logo B. Pin 1 identifier C. ESDS identification (optional) 3.2 Unit container. The unit container shall be marked with the manufacturers part number and with items A and C (
16、if applicable) above. 3.3 Electrical characteristics. The maximum and recommended operating conditions and electrical performance characteristics are as specified in 1.3, 1.4, and table I herein. 3.4 Design, construction, and physical dimension. The design, construction, and physical dimensions are
17、as specified herein. _ 3/ Stresses beyond those listed under “absolute maximum rating” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is n
18、ot implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 4/ Use of this product beyond the manufacturers design rules or stated parameters is done at the users risk. The manufacturer and/or distributor maintain no responsibility or liability for p
19、roduct used beyond the stated limits. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04607 REV A PAGE 4 3.5 Diagrams. 3.5.1 Case outline(s). The case outline(s) s
20、hall be as shown in 1.2.2 and figure 1. 3.5.2 Terminal connections. The terminal connections shall be as shown in figure 2. 3.5.3 Block diagram. The block diagram shall be as specified in figure 3. 3.5.4 Load circuit. The load circuit shall be as specified in figure 4. 3.5.5 Timing waveforms. The ti
21、ming waveforms shall be as shown in figure 5-25. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04607 REV A PAGE 5 TABLE I. Electrical performance characteristics
22、. 1/ Test Symbol Test condition -40C TC+85C 1.75 V CVDD 1.98 V 3.0 V DVDD 3.6 V unless otherwise noted Limits Unit Min Max High level output voltage 2/ VOHDVDD= 3.3 0.3 V, IOH= Max 2.4 V Low level output voltage 2/ VOLIOL= Max 0.4 V Input current in high impedance IIZDVDD= Max, VI= VSSto DVDD-10 10
23、A Input current (VI= VSSto DVDD) TRST IIWith internal pulldown -10 35 See pin descriptions With internal pullups -35 10 PPD15:0 Bus holders enabled, DVDD= Max 3/ -200 200 All other input only pins -10 10 Supply current, both core CPUs IDDCCVDD= 1.8 V, TC= 25C fX= 100 MHz 4/ 90 TYP 5/ mA Supply curre
24、nt, pins IDDPDVDD= 3.3 V, fCLOCK= 100 MHz 5/ TC= 25C 6/ 54 TYP mA Supply current, PLL IDDA5 TYP mA Supply current, standby IDLE2 IDDCPLL x n mode, 20 MHz input 2 TYP mA IDLE3 PLL x n mode, 20 MHz input 600 TYP A Input capacitance CI10 TYP pF Output capacitance CO10 TYP pF CLOCK OPTION Divide by 2 an
25、d divide by 4 clock options timing requirements Cycle time, CLKIN tc(CI)See figure 5 20 7/ ns Fall time, CLKIN tf(CI)8 Rise time, CLKIN tr(CI)8 Pulse duration, CLKIN low tW(CIL)5 Pulse duration, CLKIN high tW(CIH)5 Divide by 2 and divide by 4 clock options switching characteristics 8/ Cycle time, CL
26、KOUT tc(CO)See figure 5 40 7/ ns Cycle time, CLKOUT bypass mode tc(CO)40 7/ Delay time, CLKIN high to CLKOUT high/low td(CIH-CO)3 10 Fall time, CLKOUT tf(CO)2 Typ Rise time, CLKOUT tr(CO)2 Typ Pulse duration , CLKOUT low tW(COL)H-2 H+2 Pulse duration , CLKOUT high tW(COH)H-2 H+2 See notes at end of
27、table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04607 REV A PAGE 6 TABLE I. Electrical performance characteristics - Continued. 1/ Test Symbol Test conditio
28、n -40C TC+85C 1.75 V CVDD 1.98 V 3.0 V DVDD 3.6 V unless otherwise noted Limits Unit Min Max CLOCK OPTION (CONTINUED). Multiply by N clock option timing requirements 8/ Cycle time, CLKIN Integer PLL multiplier N (N = 1-15) 9/ tc(CI)See figure 6 20 9/ 200 ns PLL multiplier N = x.5 9/ 20 9/ 100 PLL mu
29、ltiplier N = x.5, x.75 9/ 20 9/ 50 Fall time, CLKIN tf(CI)8 Rise time, CLKIN tr(CI)8 Pulse duration, CLKIN low tW(CIL)5 Pulse duration, CLKIN high tW(CIH)5 Multiply by N clock option switching characteristics 8/ Cycle time, CLKOUT tc(CO)See figure 6 10 ns Delay time, CLKIN high/low to CLKOUT high/lo
30、w td(CI-CO)4 16 Fall time, CLKOUT tf(CO)2 Typ Rise time, CLKOUT tr(CO)2 Typ Pulse duration , CLKOUT low tW(COL)H-2 H+2 Pulse duration , CLKOUT high tW(COH)H-2 H+2 Transitory phase, PLL lock up time tp30 s EXTERNAL MEMORY INTERFACE TIMING Memory read timing requirements 14/ Access time, read data acc
31、ess from address valid 11/ ta(A)MSee figure 7 2H-12 ns Access time, read data access from MSTRB low ta(MSTRBL)2H-11 Setup time, read data before CLOCKOUT low tsu(D)R9 Hold time, read data after CLOCKOUT low th(D)R0 Hold time, read data after address invalid th(A-D)R0 Hold time, read data after MSTRB
32、 high th(D)MSTRBH0 See notes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04607 REV A PAGE 7 TABLE I. Electrical performance characteristics -
33、Continued. 1/ Test Symbol Test condition -40C TC+85C 1.75 V CVDD 1.98 V 3.0 V DVDD 3.6 V unless otherwise noted Limits Unit Min Max EXTERNAL MEMORY INTERFACE TIMING (CONTINUED) Memory read switching characteristics Delay time, CLKOUT low to address valid 11/ 12/ td(CLKL-A)See figure 7 -1 5 ns Delay
34、time, CLKOUT high (transaction) to address valid 11/ 13/ td(CLKH-A)-1 6 Delay time, CLKOUT low to MSTRB low td(CLKL-MSL)-1 4 Delay time, CLKOUT MSTRB high td(CLKL-MSH)-1 4 Hold time, address valid after CLKOUT low 11/ 12/ th(CLKL-A)R-1 5 13/ Hold time, address valid after CLKOUT lhigh 11/ 13/ th(CLK
35、H-A)R-1 6 13/ Memory write switching characteristics 14/ Delay time, CLKOUT high to address valid 11/ 15/ td(CLKH-A)See figure 8 -1 6 ns Delay time, CLKOUT low to address valid 11/ 16/ td(CLKL-A)-1 5 Delay time, CLKOUT low to MSTRB low td(CLKL-MSL)-1 4 Delay time, CLKOUT low to data valid td(CLKL-D)
36、W0 7 Delay time, CLKOUT low to MSTRB high td(CLKL-MSH)-1 4 Delay time, CLKOUT high to R/ W low td(CLKH-RWL)0 4 Delay time, CLKOUT high to R/ W high td(CLKH-RWH)0 4 Delay time, R/ W low to MSTRB low td(RWL-MSTRBL)H-2 H+2 Hold time, address valid after CLKOUT high 11/ 16/ th(A)W-1 6 Hold time, write d
37、ata valid after MSTRB high th(D)MSHH-3 H+3 16/ Pulse duration, MSTRB low 16/ tw(SL)MS2H-4 Setup time, address valid before MSTRB low 11/ tsu(A)W2H-4 Setup time, write data valid before MSTRB high tsu(D)MSH2H-5 2H+5 16/ See notes at end of table. Provided by IHSNot for ResaleNo reproduction or networ
38、king permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04607 REV A PAGE 8 TABLE I. Electrical performance characteristics - Continued. 1/ Test Symbol Test condition -40C TC+85C 1.75 V CVDD 1.98 V 3.0 V DVDD 3.6 V unless othe
39、rwise noted Limits Unit Min Max READY TIMING FOR EXTERNALLY GENERATED WAIT STATES Ready timing requirements for externally generated wait states 8/ 17/ Setup time, READY before CLKOUT low tsu(RDY)See figure 9 8 ns Hold time, READY after CLKOUT low th(RDY)0 Valid time, READY after MSTRB low 18/ tv(RD
40、Y)MSTRB2H-8 Hold time, READY after MSTRB low 18/ th(RDY)MSTRB2H PARALLEL I/O INTERFACE TIMING Parallel I/O port read timing requirements 14/ Access time, read data access from address valid 19/ ta(A)IOSee figure 10 3H-12 ns Access time, read data access from IOSTRB low ta(ISTRBL)IO2H-11 Setup time,
41、read data before CLKOUT high tsu(D)IOR9 Hold time, read data after CLKOUT high th(D)IOR0 Hold time, read data after IOSTRB high th(ISTRBH-D)R0 Parallel I/O port read switching characteristics Delay time, CLKOUT low to address valid 19/ td(CLKL-A)See figure 10 -1 5 ns Delay time, CLKOUT high to IOSTR
42、B low td(CLKH-ISTRBL)0 5 Delay time, CLKOUT high to IOSTRB high td(CLKH-ISTRBH)0 5 Hold time, address after CLKOUT low 19/ th(A)IOR-1 5 Parallel I/O port write switching characteristics Delay time, CLKOUT low to address valid 19/ td(CLKL-A)See figure 11 -1 5 ns Delay time, CLKOUT high to IOSTRB low
43、td(CLKH-ISTRBL)0 5 Delay time, CLKOUT high to write data valid td(CLKH-D)IOWH-5 H+5 Delay time, CLKOUT high to IOSTRB high td(CLKH-ISTRBH)0 5 Delay time, CLKOUT low R/ W low td(CLKL-RWL)0 4 Delay time, CLKOUT low R/ W high td(CLKL-RWH)0 4 Hold time, address valid after CLKOUT low 19/ th(A)IOW-1 5 Ho
44、ld time, write data after IOSTRB high th(D)IOWH-3 H+7 Setup time, write data before IOSTRB high tsu(D)IOSTRBHH-5 H+1 Setup time, address valid before IOSTRB low 19/ tsu(A)IOSTRBLH-5 H+3 See notes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license fr
45、om IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04607 REV A PAGE 9 TABLE I. Electrical performance characteristics - Continued. 1/ Test Symbol Test condition -40C TC+85C 1.75 V CVDD 1.98 V 3.0 V DVDD 3.6 V unless otherwise noted Limits Unit Min Max E
46、XTERNAL GENERATED WAIT STATES Externally generated wait state timing requirements 8/ 20/ Setup time, READY before CLKOUT low tsu(RDY)See figure 12 8 ns Hold time, READY after CLKOUT low th(RDY)0 Valid time, READY after IOSTRB low 18/ tv(RDY)IOSTRB3H-9 Hold time, READY after IOSTRB low 18/ th(RDY)IOS
47、TRB3H RESET, BIO , INTERRUPT, AND MP/ MC TIMINGS Reset, BIO , interrupt, and MP/ MC timing requirements 8/ Hold time, RS after CLKOUT low th(RS)See figure 13 0 ns Hold time, BIO after CLKOUT low th(BIO)0 Hold time, INTn , NMI after CLKOUT low 21/ th(INT)0 Pulse duration, RS low 22/ 23/ tw(RSL)4H+5 P
48、ulse duration, BIO low, asynchronous 21/ tw(BIO)A5H Pulse duration, INTn , NMI high (asynchronous) 21/ tw(INTH)A4H Pulse duration, INTn , NMI low (asynchronous) 21/ tw(INTL)A4H Pulse duration, INTn , NMI low for IDLE2/IDLE3 wakeup 21/ tw(INTL)WKP8 Pulse duration, XIO switched tw(XIO)4H Enable time, after XIO switched ten(XI
