1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Add footnotes to figure 4, test circuit and switching waveforms. Update boilerplate in accordance with MIL-PRF-38535 requirements. Editorial changes throughout. PHN 05-10-28 Thomas M. Hess B Update test condition VOLand VOHin table I. Update the
2、boilerplate paragraphs to the current MIL-PRF-38535 requirements. - jak 11-09-19 Thomas M. Hess REV SHEET REV SHEET REV STATUS REV B B B B B B B B B B OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 PMIC N/A PREPARED BY Monica L. Poelking DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 http:/www.landandmaritim
3、e.dla.mil/ STANDARD MICROCIRCUIT DRAWING CHECKED BY Monica L. Poelking THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS AND AGENCIES OF THE DEPARTMENT OF DEFENSE AMSC N/A APPROVED BY Michael A. Frye MICROCIRCUIT, DIGITAL, HIGH SPEED CMOS, OCTAL D-TYPE FLIP-FLOP, TTL COMPATIBLE INPUTS, MONOLITHIC
4、 SILICON DRAWING APPROVAL DATE 89-11-02 REVISION LEVEL B SIZE A CAGE CODE 67268 5962-89849 SHEET 1 OF 10 DSCC FORM 2233 APR 97 5962-E515-11 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89849 DLA LAND AND M
5、ARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 2 DSCC FORM 2234 APR 97 1. SCOPE 1.1 Scope. This drawing describes device requirements for MIL-STD-883 compliant, non-JAN class level B microcircuits in accordance with MIL-PRF-38535, appendix A. 1.2 Part or Identifying Number (PIN). The compl
6、ete PIN is as shown in the following example: 5962-89849 01 R X Drawing number Device type (see 1.2.1) Case outline (see 1.2.2) Lead finish (see 1.2.3) 1.2.1 Device type(s). The device type(s) identify the circuit function as follows: Device type Generic number Circuit function 01 54HCT534 Octal, D-
7、type flip-flops inverting, positive edge triggered, with three-state outputs and TTL compatible inputs. 1.2.2 Case outline(s). The case outline(s) are as designated in MIL-STD-1835 and as follows: Outline letter Descriptive designator Terminals Package style R GDIP1-T20 or CDIP2-T20 20 Dual-in-line
8、package 1.2.3 Lead finish. The lead finish is as specified in MIL-PRF-38535, appendix A. 1.3 Absolute maximum ratings. 1/ Supply voltage range (VCC) -0.5 V dc to +7.0 V dc DC input voltage range (VIN) -0.5 V dc to VCC+ 0.5 V dc DC output voltage range (VOUT) . -0.5 V dc to VCC+ 0.5 V dc DC input dio
9、de current (IIK) . 20 mA DC output diode current, (per pin) (IOK) 20 mA DC drain current, (per pin) (IOUT) 35 mA DC VCCor GND current (ICC, IGND) . 70 mA Storage temperature range (TSTG) -65C to +150C Maximum power dissipation (PD) . 500 mW 2/ Lead temperature (soldering, 10 seconds) . +300C Thermal
10、 resistance, junction-to-case (JC) . See MIL-STD-1835 Junction temperature (TJ) . +175C 1/ Unless otherwise specified, all voltages are referenced to ground. 2/ For TC= +100C to +125C, derate linearly at 8 mW/C Provided by IHSNot for ResaleNo reproduction or networking permitted without license from
11、 IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89849 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 3 DSCC FORM 2234 APR 97 1.4 Recommended operating conditions. Supply voltage range (VCC) +4.5 V dc to +5.5 V dc Case operating temperature range (TC) . -55C to +125C Input
12、rise or fall time (tr, tf), VCC= 4.5 V, 5.5 V 0 to 500 ns Maximum clock frequency (fMAX), VCC= 4.5 V: TC= +25C . 22 MHz TC= -55C to +125C . 16 MHz Minimum clock pulse width, (tw), VCC= 4.5 V: TC= +25C . 20 ns TC= -55C to +125C . 30 ns Minimum setup time, Dn to CP , (ts), VCC= 4.5 V: TC= +25C . 20 ns
13、 TC= -55C to +125C . 30 ns Minimum hold time, Dn to CP , (th), VCC= 4.5 V: TC= +25C . 5 ns TC= -55C to +125C . 5 ns 2. APPLICABLE DOCUMENTS 2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part of this drawing to the extent specifie
14、d herein. Unless otherwise specified, the issues of these documents are those cited in the solicitation or contract. DEPARTMENT OF DEFENSE SPECIFICATION MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-883 - Test Method Standard M
15、icrocircuits. MIL-STD-1835 - Interface Standard Electronic Component Case Outlines. DEPARTMENT OF DEFENSE HANDBOOKS MIL-HDBK-103 - List of Standard Microcircuit Drawings. MIL-HDBK-780 - Standard Microcircuit Drawings. (Copies of these documents are available online at https:/assist.daps.dla.mil/quic
16、ksearch/ or from the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.) 2.2 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text of this drawing takes precedence. Nothing in this do
17、cument, however, supersedes applicable laws and regulations unless a specific exemption has been obtained. 3. REQUIREMENTS 3.1 Item requirements. The individual item requirements shall be in accordance with MIL-PRF-38535, appendix A for non-JAN class level B devices and as specified herein. Product
18、built to this drawing that is produced by a Qualified Manufacturer Listing (QML) certified and qualified manufacturer or a manufacturer who has been granted transitional certification to MIL-PRF-38535 may be processed as QML product in accordance with the manufacturers approved program plan and qual
19、ifying activity approval in accordance with MIL-PRF-38535. This QML flow as documented in the Quality Management (QM) plan may make modifications to the requirements herein. These modifications shall not affect form, fit, or function of the device. These modifications shall not affect the PIN as des
20、cribed herein. A “Q“ or “QML“ certification mark in accordance with MIL-PRF-38535 is required to identify when the QML flow option is used. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89849 DLA LAND AND M
21、ARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 4 DSCC FORM 2234 APR 97 3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified in MIL-PRF-38535, appendix A and herein. 3.2.1 Case outline(s). The case outline(s) shall be in
22、accordance with 1.2.2 herein. 3.2.2 Terminal connections. The terminal connections shall be as specified on figure 1. 3.2.3 Truth table. The truth table shall be as specified on figure 2. 3.2.4 Logic diagram. The logic diagram shall be as specified on figure 3. 3.2.5 Test circuit and switching wavef
23、orms. The test circuit and switching waveforms shall be as specified on figure 4. 3.3 Electrical performance characteristics. Unless otherwise specified herein, the electrical performance characteristics are as specified in table I and shall apply over the full case operating temperature range. 3.4
24、Electrical test requirements. The electrical test requirements shall be the subgroups specified in table II. The electrical tests for each subgroup are described in table I. 3.5 Marking. Marking shall be in accordance with MIL-PRF-38535, appendix A. The part shall be marked with the PIN listed in 1.
25、2 herein. In addition, the manufacturers PIN may also be marked. For packages where marking of the entire SMD PIN number is not feasible due to space limitations, the manufacturer has the option of not marking the “5962-“ on the device. 3.5.1 Certification/compliance mark. A compliance indicator “C”
26、 shall be marked on all non-JAN devices built in compliance to MIL-PRF-38535, appendix A. The compliance indicator “C” shall be replaced with a “Q“ or “QML“ certification mark in accordance with MIL-PRF-38535 to identify when the QML flow option is used. 3.6 Certificate of compliance. A certificate
27、of compliance shall be required from a manufacturer in order to be listed as an approved source of supply in MIL-HDBK-103 (see 6.6 herein). The certificate of compliance submitted to DLA Land and Maritime -VA prior to listing as an approved source of supply shall affirm that the manufacturers produc
28、t meets the requirements of MIL-PRF-38535, appendix A and the requirements herein. 3.7 Certificate of conformance. A certificate of conformance as required in MIL-PRF-38535, appendix A shall be provided with each lot of microcircuits delivered to this drawing. 3.8 Notification of change. Notificatio
29、n of change to DLA Land and Maritime-VA shall be required for any change that affects this drawing. 3.9 Verification and review. DLA Land and Maritime, DLA Land and Maritime s agent, and the acquiring activity retain the option to review the manufacturers facility and applicable required documentati
30、on. Offshore documentation shall be made available onshore at the option of the reviewer. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89849 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL B
31、 SHEET 5 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics. Test Symbol Conditions 1/ -55C TC +125C unless otherwise specified 1/ Group A subgroups Limits Unit Min Max High level output voltage VOHVCC= 4.5 V VIN= VIH= 2.0 V or VIL= 0.8 V IOH= -20 A 1, 2, 3 4.4 V IOH= -6.0 mA 1, 2
32、, 3 3.7 V Low level output voltage VOLIOL= +20 A 1, 2, 3 0.1 V IOL= +6.0 mA 1, 2, 3 0.4 V High level input voltage 2/ VIHVCC= 4.5 V 1, 2, 3 2.0 V Low level input voltage 2/ VIL1, 2, 3 0.8 V Input leakage current IINVCC= 5.5 V, VIN= VCCor GND 1, 2, 3 1.0 A Quiescent supply current ICCVCC= 5.5 V, VIN=
33、 VCCor GND IOUT= 0.0 A 1, 2, 3 160 Additional quiescent supply current ICCVIN = 2.4 V, any 1 input, VIN= VCCor GND, all other inouts IOUT= 0.0 A, VCC= 5.5 V 294 Three-state output off-state current IOZVIN= 2.0 V or 0.8 V, VCC= 5.5 V VOUT= VCCor GND 1, 2, 3 10.0 Input capacitance CINSee 4.3.1c 4 10 p
34、F Three-state output capacitance COUT4 20 Functional tests See 4.3.1d 7, 8 Propagation delay time, CP to Qn tPLH, tPHL VCC= 4.5 V, CL= 50 pF See figure 4 9 35 ns 10, 11 53 Output disable time, OE to Qn tPLZ, tPHZ 9 30 10, 11 45 Output enable time, OE to Qn tPZL, tPZH 9 35 10, 11 53 Output transition
35、 time 3/ tTLH, tTHL9 12 10, 11 18 1/ For a power supply of 5.0 V 10%, the worst case output voltage (VOHand VOL) occur for HCT at VCC= 4.5 V. Thus, the 4.5 V values should be used when designing with this supply. Worst case VIHand VILoccur at VCC= 5.5 V and 4.5 V, respectively. 2/ The VIHand VILtest
36、s are not required, and shall be applied as forcing function for VOHor VOLtests. 3/ Transition time (tTLH, tTHL), if not tested, shall be guaranteed to the limits specified in table I. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIR
37、CUIT DRAWING SIZE A 5962-89849 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 6 DSCC FORM 2234 APR 97 Terminal number Terminal symbol Terminal number Terminal symbol 1 OE 11 CP 2 Q0 12 Q4 3 D0 13 D4 4 D1 14 D5 5 Q1 15 Q5 6 Q2 16 Q6 7 D2 17 D6 8 D3 18 D7 9 Q3 19 Q7 10 GND 20 V
38、CCFIGURE 1. Terminal connections. Inputs Output OE CP Dn Qn L H L L L H L L X No change H X X Z H = High voltage level L = Low voltage level Z = High impedance state = Low to high transition X = Irrelevant FIGURE 2. Truth table. FIGURE 3. Logic diagram. Provided by IHSNot for ResaleNo reproduction o
39、r networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89849 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 7 DSCC FORM 2234 APR 97 FIGURE 4. Test circuit and switching waveforms. Provided by IHSNot for ResaleNo reproduction or networkin
40、g permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89849 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 8 DSCC FORM 2234 APR 97 Notes: 1. When measuring tPLH, tPHL, tTLH, and tTHL: S1 = open, S2 open. When measuring tPZHand tPHZ: S1 = open, S2
41、= closed. When measuring tPZLand tPLZ: S1 = closed, S2 = open. 2. The waveform 1 is for an output with internal condition such that the output is low except when disabled by the output control. The waveform 2 is for an output with internal condition such that the output is high except when disabled
42、by the output control. 3. RL= 1 k or equivalent. 4. CL = 50 pF (includes test jig and probe capacitance). 5. Input signal from pulse generator: VIN= 0.0 V to 3.0 V; PRR 1 MHz; ZOUT= 50 ; tr= 6.0 ns; tf= 6.0 ns; trand tfshall be measured from 0.3 V to 2.7 V and from 2.7 V to 0.3 V, respectively; duty
43、 cycle = 50 percent. 6. The outputs are measured one at a time with one transition per measurement. FIGURE 4. Test circuit and switching waveforms - Continued. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-
44、89849 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 9 DSCC FORM 2234 APR 97 4. VERIFICATION 4.1 Sampling and inspection. Sampling and inspection procedures shall be in accordance with MIL-PRF-38535, appendix A. 4.2 Screening. Screening shall be in accordance with method 5004
45、 of MIL-STD-883, and shall be conducted on all devices prior to quality conformance inspection. The following additional criteria shall apply: a. Burn-in test, method 1015 of MIL-STD-883. (1) Test condition A, B, C, or D. The test circuit shall be maintained by the manufacturer under document revisi
46、on level control and shall be made available to the preparing or acquiring activity upon request. The test circuit shall specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in method 1015 of MIL-STD-883. (2) TA= +125C, minimum. b. Interi
47、m and final electrical test parameters shall be as specified in table II herein, except interim electrical parameter tests prior to burn-in are optional at the discretion of the manufacturer. TABLE II. Electrical test requirements. MIL-STD-883 test requirements Subgroups (in accordance with MIL-STD-
48、883, method 5005, table I) Interim electrical parameters (method 5004) - Final electrical test parameters (method 5004) 1*, 2, 3, 7, 8, 9 Group A test requirements (method 5005) 1, 2, 3, 4, 7, 8, 9, 10*, 11* Groups C and D end-point electrical parameters (method 5005) 1 * PDA applies to subgroup 1. * Subgroup 10 and 11 if not tested, shall be guaranteed to the limits specified in table I. 4.3 Quality conformance inspection. Quality conformance inspection shall be in accordance with method 5005 of
